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| author | Heiko Schocher <hs@denx.de> | 2011-09-26 13:36:54 +0200 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2011-11-03 18:27:51 -0500 |
| commit | f1ccd10672dc7f17c08fe9708c50878d479d6a7b (patch) | |
| tree | 76826c7276ad4590f24e89597fda6bb2cde75b49 | |
| parent | 4e8b750c53cc2624ecef59abfd999fae97ad8142 (diff) | |
| download | u-boot-imx-f1ccd10672dc7f17c08fe9708c50878d479d6a7b.zip u-boot-imx-f1ccd10672dc7f17c08fe9708c50878d479d6a7b.tar.gz u-boot-imx-f1ccd10672dc7f17c08fe9708c50878d479d6a7b.tar.bz2 | |
powerpc, mpc83xx: add DDR SDRAM Timing Configuration 3 definitions
Signed-off-by: Heiko Schocher <hs@denx.de>
Added its mask, too, for intra-file consistency.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| -rw-r--r-- | include/mpc83xx.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/mpc83xx.h b/include/mpc83xx.h index d345c85..aa9ce8d 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1054,6 +1054,12 @@ #define TIMING_CFG2_FOUR_ACT_SHIFT 0 /* + * TIMING_CFG_3 - DDR SDRAM Timing Configuration 3 + */ +#define TIMING_CFG3_EXT_REFREC 0x00070000 +#define TIMING_CFG3_EXT_REFREC_SHIFT 16 + +/* * DDR_SDRAM_CFG - DDR SDRAM Control Configuration */ #define SDRAM_CFG_MEM_EN 0x80000000 |