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authorPeter Tyser <ptyser@xes-inc.com>2009-07-17 10:14:48 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-07-22 09:43:48 -0500
commitd9c147f371800a479a507a816b2fe572c97da197 (patch)
tree65391575bc175d4fb20632b2f6d03fa6b47448d3
parent12a440ae6d09445140f1a0c2023dba76a9f1a617 (diff)
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85xx, 86xx: Add common board_add_ram_info()
Previously, 85xx and 86xx boards would display DRAM information on bootup such as: ... I2C: ready DRAM: Memory controller interleaving enabled: Bank interleaving! 2 GB FLASH: 256 MB ... This patch moves the printing of the DRAM controller configuration to a common board_add_ram_info() function which prints out DDR type, width, CAS latency, and ECC mode. It also makes the DDR interleaving information print out in a more sane manner: ... I2C: ready DRAM: 2 GB (DDR2, 64-bit, CL=4, ECC on) DDR Controller Interleaving Mode: bank FLASH: 256 MB ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--cpu/mpc8xxx/ddr/main.c43
-rw-r--r--cpu/mpc8xxx/ddr/util.c96
2 files changed, 98 insertions, 41 deletions
diff --git a/cpu/mpc8xxx/ddr/main.c b/cpu/mpc8xxx/ddr/main.c
index 6dae26b..faa1af9 100644
--- a/cpu/mpc8xxx/ddr/main.c
+++ b/cpu/mpc8xxx/ddr/main.c
@@ -162,28 +162,9 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
j++;
}
}
- if (j == 2) {
+ if (j == 2)
*memctl_interleaving = 1;
- printf("\nMemory controller interleaving enabled: ");
-
- switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
- case FSL_DDR_CACHE_LINE_INTERLEAVING:
- printf("Cache-line interleaving!\n");
- break;
- case FSL_DDR_PAGE_INTERLEAVING:
- printf("Page interleaving!\n");
- break;
- case FSL_DDR_BANK_INTERLEAVING:
- printf("Bank interleaving!\n");
- break;
- case FSL_DDR_SUPERBANK_INTERLEAVING:
- printf("Super bank interleaving\n");
- default:
- break;
- }
- }
-
/* Check that all controllers are rank interleaving. */
j = 0;
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
@@ -191,29 +172,9 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
j++;
}
}
- if (j == 2) {
+ if (j == 2)
*rank_interleaving = 1;
- printf("Bank(chip-select) interleaving enabled: ");
-
- switch (pinfo->memctl_opts[0].ba_intlv_ctl &
- FSL_DDR_CS0_CS1_CS2_CS3) {
- case FSL_DDR_CS0_CS1_CS2_CS3:
- printf("CS0+CS1+CS2+CS3\n");
- break;
- case FSL_DDR_CS0_CS1:
- printf("CS0+CS1\n");
- break;
- case FSL_DDR_CS2_CS3:
- printf("CS2+CS3\n");
- break;
- case FSL_DDR_CS0_CS1_AND_CS2_CS3:
- printf("CS0+CS1 and CS2+CS3\n");
- default:
- break;
- }
- }
-
if (*memctl_interleaving) {
unsigned long long addr, total_mem_per_ctlr = 0;
/*
diff --git a/cpu/mpc8xxx/ddr/util.c b/cpu/mpc8xxx/ddr/util.c
index 70dbee0..4451989 100644
--- a/cpu/mpc8xxx/ddr/util.c
+++ b/cpu/mpc8xxx/ddr/util.c
@@ -107,3 +107,99 @@ __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
unsigned int memctl_interleaved,
unsigned int ctrl_num);
+
+void board_add_ram_info(int use_default)
+{
+#if defined(CONFIG_MPC85xx)
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+#elif defined(CONFIG_MPC86xx)
+ volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
+#endif
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ uint32_t cs0_config = in_be32(&ddr->cs0_config);
+#endif
+ uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
+ int cas_lat;
+
+ puts(" (DDR");
+ switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
+ SDRAM_CFG_SDRAM_TYPE_SHIFT) {
+ case SDRAM_TYPE_DDR1:
+ puts("1");
+ break;
+ case SDRAM_TYPE_DDR2:
+ puts("2");
+ break;
+ case SDRAM_TYPE_DDR3:
+ puts("3");
+ break;
+ default:
+ puts("?");
+ break;
+ }
+
+ if (sdram_cfg & SDRAM_CFG_32_BE)
+ puts(", 32-bit");
+ else
+ puts(", 64-bit");
+
+ /* Calculate CAS latency based on timing cfg values */
+ cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
+ if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
+ cas_lat += (8 << 1);
+ printf(", CL=%d", cas_lat >> 1);
+ if (cas_lat & 0x1)
+ puts(".5");
+
+ if (sdram_cfg & SDRAM_CFG_ECC_EN)
+ puts(", ECC on)");
+ else
+ puts(", ECC off)");
+
+#if (CONFIG_NUM_DDR_CONTROLLERS > 1)
+ if (cs0_config & 0x20000000) {
+ puts("\n");
+ puts(" DDR Controller Interleaving Mode: ");
+
+ switch ((cs0_config >> 24) & 0xf) {
+ case FSL_DDR_CACHE_LINE_INTERLEAVING:
+ puts("cache line");
+ break;
+ case FSL_DDR_PAGE_INTERLEAVING:
+ puts("page");
+ break;
+ case FSL_DDR_BANK_INTERLEAVING:
+ puts("bank");
+ break;
+ case FSL_DDR_SUPERBANK_INTERLEAVING:
+ puts("super-bank");
+ break;
+ default:
+ puts("invalid");
+ break;
+ }
+ }
+#endif
+
+ if ((sdram_cfg >> 8) & 0x7f) {
+ puts("\n");
+ puts(" DDR Chip-Select Interleaving Mode: ");
+ switch(sdram_cfg >> 8 & 0x7f) {
+ case FSL_DDR_CS0_CS1_CS2_CS3:
+ puts("CS0+CS1+CS2+CS3");
+ break;
+ case FSL_DDR_CS0_CS1:
+ puts("CS0+CS1");
+ break;
+ case FSL_DDR_CS2_CS3:
+ puts("CS2+CS3");
+ break;
+ case FSL_DDR_CS0_CS1_AND_CS2_CS3:
+ puts("CS0+CS1 and CS2+CS3");
+ break;
+ default:
+ puts("invalid");
+ break;
+ }
+ }
+}