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authorTom Rini <trini@ti.com>2012-05-21 06:46:31 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-07-07 14:07:22 +0200
commitd88bc0425b333ba5baa185b4f8797be444a03f44 (patch)
treed84ad1bcb8f55a952b722a3816702ab4f537bf39
parentfe4f97b98faccc142fe6e1668ba7ff945fcf3994 (diff)
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am33xx: Fill in more cm_wkuppll / cm_perpll
Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Heiko Schocher <hs@denx.de>
-rw-r--r--arch/arm/include/asm/arch-am33xx/cpu.h40
1 files changed, 30 insertions, 10 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index 8760cc0..5a6534e 100644
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -62,7 +62,7 @@
struct cm_wkuppll {
unsigned int wkclkstctrl; /* offset 0x00 */
unsigned int wkctrlclkctrl; /* offset 0x04 */
- unsigned int resv1[1];
+ unsigned int wkgpio0clkctrl; /* offset 0x08 */
unsigned int wkl4wkclkctrl; /* offset 0x0c */
unsigned int resv2[4];
unsigned int idlestdpllmpu; /* offset 0x20 */
@@ -111,34 +111,54 @@ struct cm_perpll {
unsigned int l3clkstctrl; /* offset 0x0c */
unsigned int resv1;
unsigned int cpgmac0clkctrl; /* offset 0x14 */
- unsigned int resv2[4];
+ unsigned int lcdclkctrl; /* offset 0x18 */
+ unsigned int usb0clkctrl; /* offset 0x1C */
+ unsigned int resv2;
+ unsigned int tptc0clkctrl; /* offset 0x24 */
unsigned int emifclkctrl; /* offset 0x28 */
unsigned int ocmcramclkctrl; /* offset 0x2c */
unsigned int gpmcclkctrl; /* offset 0x30 */
- unsigned int resv3[2];
+ unsigned int mcasp0clkctrl; /* offset 0x34 */
+ unsigned int uart5clkctrl; /* offset 0x38 */
unsigned int mmc0clkctrl; /* offset 0x3C */
unsigned int elmclkctrl; /* offset 0x40 */
unsigned int i2c2clkctrl; /* offset 0x44 */
unsigned int i2c1clkctrl; /* offset 0x48 */
unsigned int spi0clkctrl; /* offset 0x4C */
unsigned int spi1clkctrl; /* offset 0x50 */
- unsigned int resv4[3];
+ unsigned int resv3[3];
unsigned int l4lsclkctrl; /* offset 0x60 */
unsigned int l4fwclkctrl; /* offset 0x64 */
- unsigned int resv5[6];
+ unsigned int mcasp1clkctrl; /* offset 0x68 */
+ unsigned int uart1clkctrl; /* offset 0x6C */
+ unsigned int uart2clkctrl; /* offset 0x70 */
+ unsigned int uart3clkctrl; /* offset 0x74 */
+ unsigned int uart4clkctrl; /* offset 0x78 */
+ unsigned int timer7clkctrl; /* offset 0x7C */
unsigned int timer2clkctrl; /* offset 0x80 */
- unsigned int resv6[11];
+ unsigned int timer3clkctrl; /* offset 0x84 */
+ unsigned int timer4clkctrl; /* offset 0x88 */
+ unsigned int resv4[8];
+ unsigned int gpio1clkctrl; /* offset 0xAC */
unsigned int gpio2clkctrl; /* offset 0xB0 */
- unsigned int resv7[7];
+ unsigned int gpio3clkctrl; /* offset 0xB4 */
+ unsigned int resv5;
+ unsigned int tpccclkctrl; /* offset 0xBC */
+ unsigned int dcan0clkctrl; /* offset 0xC0 */
+ unsigned int dcan1clkctrl; /* offset 0xC4 */
+ unsigned int resv6[2];
unsigned int emiffwclkctrl; /* offset 0xD0 */
- unsigned int resv8[2];
+ unsigned int resv7[2];
unsigned int l3instrclkctrl; /* offset 0xDC */
unsigned int l3clkctrl; /* Offset 0xE0 */
- unsigned int resv9[14];
+ unsigned int resv8[4];
+ unsigned int mmc1clkctrl; /* offset 0xF4 */
+ unsigned int mmc2clkctrl; /* offset 0xF8 */
+ unsigned int resv9[8];
unsigned int l4hsclkstctrl; /* offset 0x11C */
unsigned int l4hsclkctrl; /* offset 0x120 */
unsigned int resv10[8];
- unsigned int cpswclkctrl; /* offset 0x144 */
+ unsigned int cpswclkstctrl; /* offset 0x144 */
};
/* Encapsulating Display pll registers */