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authorPeng Fan <Peng.Fan@freescale.com>2014-09-05 10:40:11 +0800
committerPeng Fan <Peng.Fan@freescale.com>2015-04-29 15:10:28 +0800
commitbbddb98393e3ae1a35d50db4a7269a184ea1db96 (patch)
treee4b44485b0928001a2b6f1afcd6623a3f84d7985
parentd174546149b6ca341bdb638da2c0e366236f2481 (diff)
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ENGR00329484-2 ARM:MX6: Clear Align bit in SCTLR
This problem is found when debugging QuadSPI. When "A" bit is enabled, unaligned access will cause data abort exception. Actually, we do not want this exception. So clear the align bit for MX6 SOCs. Tested this code with android team colleague and did not find problem. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit aa76a7e472e34bc59554f9932d611b1047d24590)
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index eda7e12..5f66103 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -419,6 +419,9 @@ static void imx_set_pcie_phy_power_down(void)
int arch_cpu_init(void)
{
+ /* Clear the Align bit in SCTLR */
+ set_cr(get_cr() & ~CR_A);
+
#if !defined(CONFIG_MX6SX) && !defined(CONFIG_MX6SL)
/*
* imx6sl doesn't have pcie at all.