diff options
| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-04-15 16:13:47 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-05-15 16:24:26 +0200 |
| commit | b4ee1491b917951c0f57e18fd816a4211f5829d4 (patch) | |
| tree | 1b9ebaf93784b7bd0c65db38ccccd4580d84ca00 | |
| parent | d2a3e911390f9fc4d8c0ee4b3c7fc75f4fd3fd19 (diff) | |
| download | u-boot-imx-b4ee1491b917951c0f57e18fd816a4211f5829d4.zip u-boot-imx-b4ee1491b917951c0f57e18fd816a4211f5829d4.tar.gz u-boot-imx-b4ee1491b917951c0f57e18fd816a4211f5829d4.tar.bz2 | |
arm1136: move cache code from start.S to cache.c
arch/arm/cpu/arm1136/start.S contain a cache flushing function.
Remove the function and move its code into arch/arm/lib/cache.c.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
| -rw-r--r-- | arch/arm/cpu/arm1136/start.S | 10 | ||||
| -rw-r--r-- | arch/arm/lib/cache.c | 13 |
2 files changed, 10 insertions, 13 deletions
diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 3e2358e..0085754 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -333,14 +333,4 @@ fiq: bl do_fiq #endif - .align 5 -.global arm1136_cache_flush -arm1136_cache_flush: -#if !defined(CONFIG_SYS_ICACHE_OFF) - mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache -#endif -#if !defined(CONFIG_SYS_DCACHE_OFF) - mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache -#endif - mov pc, lr @ back to caller #endif /* CONFIG_SPL_BUILD */ diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 6cc136a..4f6b9f0 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -12,16 +12,23 @@ void __flush_cache(unsigned long start, unsigned long size) { #if defined(CONFIG_ARM1136) - void arm1136_cache_flush(void); - arm1136_cache_flush(); +#if !defined(CONFIG_SYS_ICACHE_OFF) + asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */ #endif + +#if !defined(CONFIG_SYS_DCACHE_OFF) + asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */ +#endif + +#endif /* CONFIG_ARM1136 */ + #ifdef CONFIG_ARM926EJS /* test and clean, page 2-23 of arm926ejs manual */ asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); -#endif +#endif /* CONFIG_ARM926EJS */ return; } void flush_cache(unsigned long start, unsigned long size) |