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authorStefan Roese <sr@denx.de>2014-11-07 13:50:32 +0100
committerMarek Vasut <marex@denx.de>2014-12-06 13:52:47 +0100
commitae79e2d2982afabd43c2121fe1c40460547a5347 (patch)
tree8d416f174fd9fdf046fc1672c9652da445a78378
parent5bef6fd79f9442269c6a0d3778cb65c7a71e4d9a (diff)
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arm: socfpga: dts: Add spi0/1 dts nodes for the Designware master SPI devices
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
-rw-r--r--arch/arm/dts/socfpga.dtsi28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/dts/socfpga.dtsi b/arch/arm/dts/socfpga.dtsi
index 145e125..969e5ad 100644
--- a/arch/arm/dts/socfpga.dtsi
+++ b/arch/arm/dts/socfpga.dtsi
@@ -643,6 +643,34 @@
status = "disabled";
};
+ spi0: spi@fff00000 {
+ compatible = "snps,dw-spi-mmio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfff00000 0x1000>;
+ interrupts = <0 154 4>;
+ num-chipselect = <4>;
+ bus-num = <0>;
+ tx-dma-channel = <&pdma 16>;
+ rx-dma-channel = <&pdma 17>;
+ clocks = <&per_base_clk>;
+ status = "disabled";
+ };
+
+ spi1: spi@fff01000 {
+ compatible = "snps,dw-spi-mmio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xfff01000 0x1000>;
+ interrupts = <0 156 4>;
+ num-chipselect = <4>;
+ bus-num = <1>;
+ tx-dma-channel = <&pdma 20>;
+ rx-dma-channel = <&pdma 21>;
+ clocks = <&per_base_clk>;
+ status = "disabled";
+ };
+
/* Local timer */
timer@fffec600 {
compatible = "arm,cortex-a9-twd-timer";