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authorHelmut Raiger <helmut.raiger@hale.at>2011-10-27 01:31:14 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2011-11-03 22:56:20 +0100
commita6d9de436c3930addf98a54f62d936426a9917a4 (patch)
tree0ab2e22a933a728a27db4e60d6531963cbb11d11
parentd121d20195aca8c7bd76f1ba67ee84f8964330c4 (diff)
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mx31: add ESD control registers
This allows to initialize DDR memory in C code. Currently all mx31 boards use assembler code (lowlevel_init.S) Signed-off-by: Helmut Raiger <helmut.raiger@hale.at> Acked-by: Stefano Babic <sbabic@denx.de>
-rw-r--r--arch/arm/include/asm/arch-mx31/imx-regs.h13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index f487975..afdaa1c 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -522,6 +522,17 @@ struct mx31_weim {
struct mx31_weim_cscr cscr[6];
};
+/* ESD control registers */
+struct esdc_regs {
+ u32 ctl0;
+ u32 cfg0;
+ u32 ctl1;
+ u32 cfg1;
+ u32 misc;
+ u32 dly[5];
+ u32 dlyl;
+};
+
#endif
#define __REG(x) (*((volatile u32 *)(x)))
@@ -600,6 +611,8 @@ struct mx31_weim {
#define ESDCTL_BL(x) ((x) << 7)
#define ESDCTL_PRCT(x) ((x) << 0)
+#define ESDCTL_BASE_ADDR 0xB8001000
+
/* 13 fields of the upper CS control register */
#define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
cnc, wsc, ew, wws, edc) \