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authorRoy Zang <tie-fei.zang@freescale.com>2013-03-25 07:33:15 +0000
committerAndy Fleming <afleming@freescale.com>2013-05-14 16:00:25 -0500
commit9458f6d83a3b44df1c2ae5c763c4f9fd6e2f9c05 (patch)
tree9538eddba53eddde5398ec18d4cbbcf339770094
parent3e4c3137d6aefaf45a87bbad701fc336f3f24a3d (diff)
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T4/serdes: fix the serdes clock frequency
Reverse the bit sequence to set and display serdes clock frequency correctly. The correct bit maps in BRDCFG2 are 0 1 2 3 4 5 6 7 S1RATE[1:0] S2RATE[1:0] S3RATE[1:0] S4RATE[1:0] Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
-rw-r--r--board/freescale/t4qds/t4qds.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/board/freescale/t4qds/t4qds.c b/board/freescale/t4qds/t4qds.c
index 3c95f3f..737d650 100644
--- a/board/freescale/t4qds/t4qds.c
+++ b/board/freescale/t4qds/t4qds.c
@@ -110,7 +110,7 @@ int checkboard(void)
for (i = 0; i < MAX_SERDES; i++) {
static const char *freq[] = {
"100", "125", "156.25", "161.1328125"};
- unsigned int clock = (sw >> (2 * i)) & 3;
+ unsigned int clock = (sw >> (6 - 2 * i)) & 3;
printf("SERDES%u=%sMHz ", i+1, freq[clock]);
}
@@ -357,7 +357,7 @@ int misc_init_r(void)
sw = QIXIS_READ(brdcfg[2]);
for (i = 0; i < MAX_SERDES; i++) {
- unsigned int clock = (sw >> (2 * i)) & 3;
+ unsigned int clock = (sw >> (6 - 2 * i)) & 3;
switch (clock) {
case 0:
actual[i] = SRDS_PLLCR0_RFCK_SEL_100;