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authorWolfgang Denk <wd@atlas.denx.de>2006-10-08 22:19:41 +0200
committerWolfgang Denk <wd@atlas.denx.de>2006-10-08 22:19:41 +0200
commit9444b8818f1de25dfa322cbe3a283c758a3d20e3 (patch)
treeae66726f706bfb5568a667117c6e9758d2214f23
parenteac5ba3e59187bb0d7d36c624851235fa850ccd1 (diff)
parentac611700e5bcdd5a762dcc4d28db256fcc5a4bf2 (diff)
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Merge with git+ssh://fifi/home/wd/git/u-boot/master
-rw-r--r--CHANGELOG3
-rw-r--r--include/ppc440.h4
2 files changed, 5 insertions, 2 deletions
diff --git a/CHANGELOG b/CHANGELOG
index ab3c590..31233b7 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
Changes since U-Boot 1.1.4:
======================================================================
+* Fix comments in include/ppc440.h
+ Patch by Martin Hicks, 16 Jun 2006
+
* Update for CAM5200 board:
- Map in a additional chip selects CS4 and CS5.
- Modify the port configration, configure six UARTs and no PCI,
diff --git a/include/ppc440.h b/include/ppc440.h
index c4a3ed5..e407320 100644
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1570,8 +1570,8 @@
#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */
#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */
#if defined(CONFIG_440GX)
-#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 0 Channel table pointer reg */
-#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 1 Channel table pointer reg */
+#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table pointer reg */
+#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table pointer reg */
#endif /* CONFIG_440GX */
#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */
#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */