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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-12-17 11:09:34 +0800 |
|---|---|---|
| committer | guoyin.chen <guoyin.chen@freescale.com> | 2016-03-04 15:53:35 +0800 |
| commit | 907059ee67e2bf5594e3d82487b40e6fa17b4d11 (patch) | |
| tree | 1ba3e01dbc750448c0acd2883316d715502c14f5 | |
| parent | ddf4e63c361fe8c4488b73e3b9db575ea5207d66 (diff) | |
| download | u-boot-imx-907059ee67e2bf5594e3d82487b40e6fa17b4d11.zip u-boot-imx-907059ee67e2bf5594e3d82487b40e6fa17b4d11.tar.gz u-boot-imx-907059ee67e2bf5594e3d82487b40e6fa17b4d11.tar.bz2 | |
MLK-12030: imx: mx7d: fix the temperature checking for TO1.1
We can rely on finish bit for temperature reading for TO1.1.
Also introduce CHIP_REV_xx macros for 7D.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| -rw-r--r-- | arch/arm/include/asm/arch-mx7/imx-regs.h | 2 | ||||
| -rw-r--r-- | drivers/thermal/imx_thermal.c | 33 |
2 files changed, 26 insertions, 9 deletions
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index ee56426..532b0da 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -216,6 +216,8 @@ #define FEC_QUIRK_ENET_MAC #define SNVS_LPGPR 0x68 +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 5d7a1a8..5a1caf2 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -12,6 +12,8 @@ #include <fuse.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> #include <dm.h> #include <errno.h> #include <malloc.h> @@ -126,6 +128,7 @@ static int read_cpu_temperature(struct udevice *dev) #define TEMPERATURE_HOT 85 #define TEMPERATURE_MAX 125 #define MEASURE_FREQ 327 +#define TEMPSENSE1_FINISHED (1 << 11) static int read_cpu_temperature(struct udevice *dev) { @@ -168,18 +171,30 @@ static int read_cpu_temperature(struct udevice *dev) writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set); - start = get_timer(0); - /* Wait max 100ms */ - do { - /* - * Since we can not rely on finish bit, use 1ms delay to get - * temperature. From RM, 17us is enough to get data, but - * to gurantee to get the data, delay 100ms here. - */ + if (is_soc_rev(CHIP_REV_1_1) >= 0) { + /* make sure that the latest temp is valid */ + while ((readl(&ccm_anatop->tempsense1) & + TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0) + udelay(10000); reg = readl(&ccm_anatop->tempsense1); tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; - } while (get_timer(0) < (start + 100)); + } else { + start = get_timer(0); + /* Wait max 100ms */ + do { + /* + * Since we can not rely on finish bit, use 100ms + * delay to get temperature. From RM, 17us is + * enough to get data, but to gurantee to get + * the data, delay 100ms here. + */ + reg = readl(&ccm_anatop->tempsense1); + tmp = (reg & + TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) + >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; + } while (get_timer(0) < (start + 100)); + } writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); |