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authoryork <yorksun@freescale.com>2010-07-02 22:25:54 +0000
committerKumar Gala <galak@kernel.crashing.org>2010-07-26 13:16:09 -0500
commit7fd101c97b58dab7b0bd87f30c3dedb0db21d15f (patch)
treefe0f75ff8b46b1bc0367f6c600418a596eaee446
parent5800e7ab32c200836e81ab2384817d93105561c5 (diff)
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powerpc/8xxx: Enabled address hashing for 85xx
For 85xx silicon which supports address hashing, it can be activated by hwconfig. Signed-off-by: York Sun <yorksun@freescale.com>
-rw-r--r--arch/powerpc/cpu/mpc85xx/ddr-gen3.c2
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c10
-rw-r--r--arch/powerpc/cpu/mpc8xxx/ddr/options.c7
-rw-r--r--arch/powerpc/include/asm/fsl_ddr_sdram.h2
-rw-r--r--doc/README.fsl-ddr15
5 files changed, 34 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index 0691ca4..e46dcb7 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -33,6 +33,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
return;
}
+ out_be32(&ddr->eor, regs->ddr_eor);
+
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (i == 0) {
out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 6e73b1d..ff0ddd1 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -1161,6 +1161,14 @@ static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr)
);
}
+static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
+{
+ if (popts->addr_hash) {
+ ddr->ddr_eor = 0x40000000; /* address hash enable */
+ puts("Addess hashing enabled.\n");
+ }
+}
+
unsigned int
check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
{
@@ -1392,6 +1400,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_csn_config_2(i, ddr);
}
+ set_ddr_eor(ddr, popts);
+
#if !defined(CONFIG_FSL_DDR1)
set_timing_cfg_0(ddr);
#endif
diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/options.c b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
index 1d5f3e2..e4805d3 100644
--- a/arch/powerpc/cpu/mpc8xxx/ddr/options.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/options.c
@@ -341,6 +341,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
}
}
+ if (hwconfig_sub("fsl_ddr", "addr_hash")) {
+ if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "null"))
+ popts->addr_hash = 0;
+ else if (hwconfig_subarg_cmp("fsl_ddr", "addr_hash", "true"))
+ popts->addr_hash = 1;
+ }
+
if (pdimm[0].n_ranks == 4)
popts->quad_rank_present = 1;
diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h
index 431327e..d576eb8 100644
--- a/arch/powerpc/include/asm/fsl_ddr_sdram.h
+++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h
@@ -119,6 +119,7 @@ typedef struct fsl_ddr_cfg_regs_s {
unsigned int ddr_sr_cntr;
unsigned int ddr_sdram_rcw_1;
unsigned int ddr_sdram_rcw_2;
+ unsigned int ddr_eor;
} fsl_ddr_cfg_regs_t;
typedef struct memctl_options_partial_s {
@@ -156,6 +157,7 @@ typedef struct memctl_options_s {
unsigned int memctl_interleaving;
unsigned int memctl_interleaving_mode;
unsigned int ba_intlv_ctl;
+ unsigned int addr_hash;
/* Operational mode parameters */
unsigned int ECC_mode; /* Use ECC? */
diff --git a/doc/README.fsl-ddr b/doc/README.fsl-ddr
index 8c37bbe..e108a0d 100644
--- a/doc/README.fsl-ddr
+++ b/doc/README.fsl-ddr
@@ -71,5 +71,16 @@ The ways to configure the ddr interleaving mode
# bank(chip-select) interleaving (cs0+cs1+cs2+cs3) (4x1)
setenv hwconfig "fsl_ddr:bank_intlv=cs0_cs1_cs2_cs3"
- The above memory controller interleaving and bank interleaving can be mixed. The syntax is
- setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1"
+Memory controller address hashing
+==================================
+If the DDR controller supports address hashing, it can be enabled by hwconfig.
+
+Syntax is:
+hwconfig=fsl_ddr:addr_hash=true
+
+Combination of hwconfig
+=======================
+Hwconfig can be combined with multiple parameters, for example, on a supported
+platform
+
+hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3