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authorYork Sun <yorksun@freescale.com>2013-03-25 07:33:27 +0000
committerAndy Fleming <afleming@freescale.com>2013-05-14 16:00:29 -0500
commit615f0cba584d11944b43af03cc6d9324fc7587e3 (patch)
treee2f0639298f97b9fbc2f132de878d7f28389cd83
parenteb80880eb2806eea4436e9ee7fd8a8b741ee0620 (diff)
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powerpc/mpc85xx: Fix PIR parsing for chassis2
The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
-rw-r--r--arch/powerpc/cpu/mpc85xx/release.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/release.S b/arch/powerpc/cpu/mpc85xx/release.S
index 0dea871..467ea10 100644
--- a/arch/powerpc/cpu/mpc85xx/release.S
+++ b/arch/powerpc/cpu/mpc85xx/release.S
@@ -159,9 +159,9 @@ __secondary_start_page:
* we cannot access it yet before setting up a new TLB
*/
mfspr r0,SPRN_PIR
-#if defined(CONFIG_E6500)
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
/*
- * PIR definition for E6500
+ * PIR definition for Chassis 2
* 0-17 Reserved (logic 0s)
* 8-19 CHIP_ID, 2'b00 - SoC 1
* all others - reserved
@@ -187,7 +187,7 @@ __secondary_start_page:
slwi r8,r4,6 /* spin table is padded to 64 byte */
add r10,r3,r8
-#ifdef CONFIG_E6500
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
mfspr r0,SPRN_PIR
/*
* core 0 thread 0: pir reset value 0x00, new pir 0