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authorWolfgang Denk <wd@denx.de>2008-05-03 20:46:40 +0200
committerWolfgang Denk <wd@denx.de>2008-05-03 20:46:40 +0200
commit56bb37e4b92b690d76026133f26cb7a640c8d5bb (patch)
tree7afe9a6c4547af9fe813e88f7b08e4be864f3eb2
parent0072b78be2b41e5a0ca3ddc39335574dc2e855bd (diff)
parent4f27098e5b0736989b13cd61d7bca94b3574cf5f (diff)
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Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
-rw-r--r--cpu/ppc4xx/44x_spd_ddr2.c7
-rw-r--r--nand_spl/board/amcc/canyonlands/ddr2_fixed.c12
2 files changed, 12 insertions, 7 deletions
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 5b5de48..ec76b71 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -1,7 +1,10 @@
/*
* cpu/ppc4xx/44x_spd_ddr2.c
* This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
- * DDR2 controller (non Denali Core). Those are 440SP/SPe.
+ * DDR2 controller (non Denali Core). Those currently are:
+ *
+ * 405: 405EX
+ * 440/460: 440SP/440SPe/460EX/460GT
*
* (C) Copyright 2007-2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
@@ -2078,7 +2081,7 @@ static void program_bxcf(unsigned long *dimm_populated,
if (num_banks == 4)
ind = 0;
else
- ind = 5;
+ ind = 5 << 8;
switch (num_col_addr) {
case 0x08:
mode |= (SDRAM_BXCF_M_AM_0 + ind);
diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c
index 79f3b0f..9010fca 100644
--- a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c
+++ b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c
@@ -49,20 +49,21 @@ long int initdram(int board_type)
* enabled. This will only work for the same memory
* configuration as used here:
*
- * Crucial CT6464AC53E.4FE - 512MB SO-DIMM
+ * Crucial CT6464AC667.8FB - 512MB SO-DIMM
*
*/
mtsdram(SDRAM_MCOPT2, 0x00000000);
- mtsdram(SDRAM_MCOPT1, 0x05322000);
+ mtsdram(SDRAM_MCOPT1, 0x05122000);
mtsdram(SDRAM_MODT0, 0x01000000);
- mtsdram(SDRAM_CODT, 0x00800021);
+ mtsdram(SDRAM_CODT, 0x02800021);
mtsdram(SDRAM_WRDTR, 0x82000823);
mtsdram(SDRAM_CLKTR, 0x40000000);
mtsdram(SDRAM_MB0CF, 0x00000201);
+ mtsdram(SDRAM_MB1CF, 0x00000201);
mtsdram(SDRAM_RTR, 0x06180000);
mtsdram(SDRAM_SDTR1, 0x80201000);
mtsdram(SDRAM_SDTR2, 0x42103243);
- mtsdram(SDRAM_SDTR3, 0x0A0D0D1A);
+ mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
mtsdram(SDRAM_MMODE, 0x00000632);
mtsdram(SDRAM_MEMODE, 0x00000040);
mtsdram(SDRAM_INITPLR0, 0xB5380000);
@@ -86,7 +87,8 @@ long int initdram(int board_type)
wait_init_complete();
- mtdcr(SDRAM_R0BAS, 0x0000F000); /* MQ0_B0BAS */
+ mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
+ mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */
mtsdram(SDRAM_RDCC, 0x40000000);
mtsdram(SDRAM_RQDC, 0x80000038);