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| author | Robin Gong <yibin.gong@nxp.com> | 2016-02-02 16:54:35 +0800 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2016-05-23 15:43:42 -0500 |
| commit | 568ea7b6a7a0c02d44df44b90e94fb9861c37897 (patch) | |
| tree | 8a4b60b31e64231cd84bf6a11667a120201cf0c6 | |
| parent | 148ec2bf7053e093fda5598077acd41323721ee9 (diff) | |
| download | u-boot-imx-568ea7b6a7a0c02d44df44b90e94fb9861c37897.zip u-boot-imx-568ea7b6a7a0c02d44df44b90e94fb9861c37897.tar.gz u-boot-imx-568ea7b6a7a0c02d44df44b90e94fb9861c37897.tar.bz2 | |
MLK-12371-1: imx: mx7d_12x12_lpddr3_arm2: fix POR reset failed after DDR enter retention
Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR
retention mode before uboot boot, so add this in DCD and plugin code. Meanwhile
correct the HW_ANADIG_SNVS_MISC_CTRL setting to avoid touching other bits.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
| -rw-r--r-- | board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg | 3 | ||||
| -rw-r--r-- | board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg | 3 | ||||
| -rw-r--r-- | board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S | 13 |
3 files changed, 17 insertions, 2 deletions
diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg index 3c4ace4..c0da271 100644 --- a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage.cfg @@ -51,6 +51,9 @@ CSF CONFIG_CSF_SIZE */ DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 DATA 4 0x30391000 0x00000002 DATA 4 0x307a0000 0x03040008 diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg index 00a74f7..e38c44c 100644 --- a/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/imximage_TO_1_1.cfg @@ -51,6 +51,9 @@ CSF CONFIG_CSF_SIZE */ DATA 4 0x30340004 0x4F400005 +/* Clear then set bit30 to ensure exit from DDR retention */ +DATA 4 0x30360388 0x40000000 +DATA 4 0x30360384 0x40000000 DATA 4 0x30391000 0x00000002 DATA 4 0x307a0000 0x03040008 diff --git a/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S index a097799..aaf65c2 100644 --- a/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S +++ b/board/freescale/mx7d_12x12_lpddr3_arm2/plugin.S @@ -85,7 +85,7 @@ TUNE_END: /* turn on ddr power */ ldr r7, =(0x1 << 29) - str r7, [r1, #0x380] + str r7, [r1, #0x388] ldr r6, =50 1: @@ -246,8 +246,11 @@ TUNE_END: bic r7, r7, #(1 << 29) str r7, [r11] 2: + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ ldr r7, =(0x1 << 30) - str r7, [r1, #0x380] + str r7, [r1, #0x388] + ldr r7, =(0x1 << 30) + str r7, [r1, #0x384] /* need to delay ~5mS */ ldr r6, =0x100000 @@ -414,6 +417,12 @@ TUNE_END: ldr r1, =0x4f400005 str r1, [r0, #0x4] + /* clear/set bit30 of SNVS_MISC_CTRL to ensure exit from ddr retention */ + ldr r0, =ANATOP_BASE_ADDR + ldr r1, =(0x1 << 30) + str r1, [r0, #0x388] + str r1, [r0, #0x384] + ldr r0, =SRC_BASE_ADDR ldr r1, =0x2 ldr r2, =0x1000 |