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authorDavid Brownell <david-b@pacbell.net>2008-01-18 12:55:00 -0800
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-03-30 15:38:05 +0200
commit480ed1dea103a1c8f4591afc77d2de3c7868d983 (patch)
tree3742d043b46f92c9767505d92e6f1ace8bd66954
parenta3543d6dc52b0ba9c64016687cf32d600b31a476 (diff)
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use correct at91rm9200 register name
This fixes a naming bug for at91rm9200 lowlevel init code: NOR boot flash is on chipselect 0, not chipselect 2. This makes code use the register name from chip datasheets. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
-rw-r--r--cpu/arm920t/at91rm9200/lowlevel_init.S6
-rw-r--r--include/configs/at91rm9200dk.h2
-rw-r--r--include/configs/cmc_pu2.h2
-rw-r--r--include/configs/csb637.h2
-rw-r--r--include/configs/mp2usb.h2
5 files changed, 7 insertions, 7 deletions
diff --git a/cpu/arm920t/at91rm9200/lowlevel_init.S b/cpu/arm920t/at91rm9200/lowlevel_init.S
index 1902bd0..98363eb 100644
--- a/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ b/cpu/arm920t/at91rm9200/lowlevel_init.S
@@ -46,7 +46,7 @@
#define MC_ASR 0xFFFFFF04
#define MC_AASR 0xFFFFFF08
#define EBI_CFGR 0xFFFFFF64
-#define SMC2_CSR 0xFFFFFF70
+#define SMC_CSR0 0xFFFFFF70
/* clocks */
#define PLLAR 0xFFFFFC28
@@ -146,8 +146,8 @@ SMRDATA:
.word MC_AASR_VAL
.word EBI_CFGR
.word EBI_CFGR_VAL
- .word SMC2_CSR
- .word SMC2_CSR_VAL
+ .word SMC_CSR0
+ .word SMC_CSR0_VAL
.word PLLAR
.word PLLAR_VAL
.word PLLBR
diff --git a/include/configs/at91rm9200dk.h b/include/configs/at91rm9200dk.h
index 5b7212a..951ce16 100644
--- a/include/configs/at91rm9200dk.h
+++ b/include/configs/at91rm9200dk.h
@@ -51,7 +51,7 @@
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
-#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
diff --git a/include/configs/cmc_pu2.h b/include/configs/cmc_pu2.h
index d22d350..bce5fcd 100644
--- a/include/configs/cmc_pu2.h
+++ b/include/configs/cmc_pu2.h
@@ -50,7 +50,7 @@
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
-#define SMC2_CSR_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL 0x100032ad /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x2026BE04 /* 179,712 MHz for PCK */
diff --git a/include/configs/csb637.h b/include/configs/csb637.h
index f93c3bc..e9c6d8e 100644
--- a/include/configs/csb637.h
+++ b/include/configs/csb637.h
@@ -51,7 +51,7 @@
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
-#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x2031BE01 /* 184.320000 MHz for PCK */
diff --git a/include/configs/mp2usb.h b/include/configs/mp2usb.h
index 294221f..2eb4af1 100644
--- a/include/configs/mp2usb.h
+++ b/include/configs/mp2usb.h
@@ -55,7 +55,7 @@
#define MC_ASR_VAL 0x00000000
#define MC_AASR_VAL 0x00000000
#define EBI_CFGR_VAL 0x00000000
-#define SMC2_CSR_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
+#define SMC_CSR0_VAL 0x00003084 /* 16bit, 2 TDF, 4 WS */
/* clocks */
#define PLLAR_VAL 0x20263E04 /* 180 MHz for PCK */