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authorChin Liang See <clsee@altera.com>2014-07-22 04:28:35 -0500
committerTom Rini <trini@ti.com>2014-08-29 15:50:54 -0400
commit3ab019e1dc39c69ae7fd0e15b080ef6c59cd138f (patch)
treee9832b3f75646bdeb80e9fe1bc4a8bbce01b65ac
parent51fb455f82b08ef1bf21b5c51181d26fef56df03 (diff)
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socfpga: Fix SOCFPGA build error for Altera dev kit
To fix the build error when build for Altera dev kit, not virtual target. At same time, set the build for Altera dev kit as default instead virtual target. With that, U-Boot is booting well and SPL still lack of few drivers. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
-rw-r--r--arch/arm/cpu/armv7/socfpga/clock_manager.c1
-rw-r--r--arch/arm/cpu/armv7/socfpga/config.mk3
-rw-r--r--arch/arm/cpu/armv7/socfpga/spl.c2
-rw-r--r--arch/arm/include/asm/arch-socfpga/scan_manager.h2
-rw-r--r--board/altera/socfpga/Makefile2
-rw-r--r--include/configs/socfpga_cyclone5.h2
6 files changed, 9 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv7/socfpga/clock_manager.c b/arch/arm/cpu/armv7/socfpga/clock_manager.c
index 0228ac8..158501a 100644
--- a/arch/arm/cpu/armv7/socfpga/clock_manager.c
+++ b/arch/arm/cpu/armv7/socfpga/clock_manager.c
@@ -188,7 +188,6 @@ void cm_basic_init(const cm_config_t *cfg)
* Time starts here
* must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
*/
- reset_timer();
start = get_timer(0);
/* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
timeout = 7;
diff --git a/arch/arm/cpu/armv7/socfpga/config.mk b/arch/arm/cpu/armv7/socfpga/config.mk
index 3d18491..2a99c72 100644
--- a/arch/arm/cpu/armv7/socfpga/config.mk
+++ b/arch/arm/cpu/armv7/socfpga/config.mk
@@ -6,3 +6,6 @@
ifndef CONFIG_SPL_BUILD
ALL-y += u-boot.img
endif
+
+# Added for handoff support
+PLATFORM_RELFLAGS += -Iboard/$(VENDOR)/$(BOARD)
diff --git a/arch/arm/cpu/armv7/socfpga/spl.c b/arch/arm/cpu/armv7/socfpga/spl.c
index 4bed19d..27efde6 100644
--- a/arch/arm/cpu/armv7/socfpga/spl.c
+++ b/arch/arm/cpu/armv7/socfpga/spl.c
@@ -14,6 +14,8 @@
#include <spl.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/freeze_controller.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/scan_manager.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/include/asm/arch-socfpga/scan_manager.h b/arch/arm/include/asm/arch-socfpga/scan_manager.h
index f9be621..b2686d3 100644
--- a/arch/arm/include/asm/arch-socfpga/scan_manager.h
+++ b/arch/arm/include/asm/arch-socfpga/scan_manager.h
@@ -87,4 +87,6 @@ extern const uint32_t iocsr_scan_chain2_table[
extern const uint32_t iocsr_scan_chain3_table[
((CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH / 32) + 1)];
+int scan_mgr_configure_iocsr(void);
+
#endif /* _SCAN_MANAGER_H_ */
diff --git a/board/altera/socfpga/Makefile b/board/altera/socfpga/Makefile
index de339ec..44baa00 100644
--- a/board/altera/socfpga/Makefile
+++ b/board/altera/socfpga/Makefile
@@ -7,4 +7,4 @@
#
obj-y := socfpga_cyclone5.o
-obj-$(CONFIG_SPL_BUILD) += pinmux_config.o
+obj-$(CONFIG_SPL_BUILD) += pinmux_config.o iocsr_config.o
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 27c2be9..e02b50a 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -15,7 +15,7 @@
* High level configuration
*/
/* Virtual target or real hardware */
-#define CONFIG_SOCFPGA_VIRTUAL_TARGET
+#undef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_ARMV7
#define CONFIG_SYS_DCACHE_OFF