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authorWolfgang Denk <wd@denx.de>2008-04-26 00:06:13 +0200
committerWolfgang Denk <wd@denx.de>2008-04-26 00:06:13 +0200
commit1d907e66fdd5d2f192a9f4fad6812ff0d0e9683a (patch)
tree59e09371286cb870fafad2c88d796062ba540447
parentd0d91ae3acb4f29d1a2a3a766747478ed54e2848 (diff)
parent8e048c438e20ec89b49da5f085f8f756eba6e587 (diff)
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Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xx
-rw-r--r--board/esd/apc405/apc405.c7
-rw-r--r--cpu/ppc4xx/fdt.c42
-rw-r--r--include/asm-ppc/4xx_pcie.h5
-rw-r--r--include/configs/APC405.h14
4 files changed, 64 insertions, 4 deletions
diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
index b663184..2cb743e 100644
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -385,11 +385,16 @@ int misc_init_r(void)
}
out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
- if (getenv("usb_self") == NULL) {
+ /*
+ * fix environment for field updated units
+ */
+ if (getenv("altbootcmd") == NULL) {
setenv("usb_load", CFG_USB_LOAD_COMMAND);
setenv("usbargs", CFG_USB_ARGS);
setenv("bootcmd", CONFIG_BOOTCOMMAND);
setenv("usb_self", CFG_USB_SELF_COMMAND);
+ setenv("bootlimit", CFG_BOOTLIMIT);
+ setenv("altbootcmd", CFG_ALT_BOOTCOMMAND);
saveenv();
}
diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c
index afcb974..1f4d6f2 100644
--- a/cpu/ppc4xx/fdt.c
+++ b/cpu/ppc4xx/fdt.c
@@ -31,9 +31,46 @@
#include <libfdt.h>
#include <libfdt_env.h>
#include <fdt_support.h>
+#include <asm/4xx_pcie.h>
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Fixup all PCIe nodes by setting the device_type property
+ * to "pci-endpoint" instead is "pci" for endpoint ports.
+ * This property will get checked later by the Linux driver
+ * to properly configure the PCIe port in Linux (again).
+ */
+void fdt_pcie_setup(void *blob)
+{
+ const char *compat = "ibm,plb-pciex";
+ const char *prop = "device_type";
+ const char *prop_val = "pci-endpoint";
+ const u32 *port;
+ int no;
+ int rc;
+
+ /* Search first PCIe node */
+ no = fdt_node_offset_by_compatible(blob, -1, compat);
+ while (no != -FDT_ERR_NOTFOUND) {
+ port = fdt_getprop(blob, no, "port", NULL);
+ if (port == NULL) {
+ printf("WARNING: could not find port property\n");
+ } else {
+ if (is_end_point(*port)) {
+ rc = fdt_setprop(blob, no, prop, prop_val,
+ strlen(prop_val) + 1);
+ if (rc < 0)
+ printf("WARNING: could not set %s for %s: %s.\n",
+ prop, compat, fdt_strerror(rc));
+ }
+ }
+
+ /* Jump to next PCIe node */
+ no = fdt_node_offset_by_compatible(blob, no, compat);
+ }
+}
+
void ft_cpu_setup(void *blob, bd_t *bd)
{
sys_info_t sys_info;
@@ -60,5 +97,10 @@ void ft_cpu_setup(void *blob, bd_t *bd)
* Note: aliases in the dts are required for this
*/
fdt_fixup_ethernet(blob, bd);
+
+ /*
+ * Fixup all available PCIe nodes by setting the device_type property
+ */
+ fdt_pcie_setup(blob);
}
#endif /* CONFIG_OF_LIBFDT */
diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h
index d27d2a9..5398696 100644
--- a/include/asm-ppc/4xx_pcie.h
+++ b/include/asm-ppc/4xx_pcie.h
@@ -8,10 +8,11 @@
* option) any later version.
*/
-#include <ppc4xx.h>
#ifndef __4XX_PCIE_H
#define __4XX_PCIE_H
+#include <ppc4xx.h>
+
#define DCRN_SDR0_CFGADDR 0x00e
#define DCRN_SDR0_CFGDATA 0x00f
@@ -395,6 +396,7 @@ static inline void mdelay(int n)
udelay(1000);
}
+#if defined(PCIE0_SDR)
static inline u32 sdr_base(int port)
{
switch (port) {
@@ -409,5 +411,6 @@ static inline u32 sdr_base(int port)
#endif
}
}
+#endif /* defined(PCIE0_SDR) */
#endif /* __4XX_PCIE_H */
diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index e2ab39d..8ad33f1 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -48,6 +48,7 @@
#define CONFIG_BAUDRATE 115200
#define CONFIG_BOOTDELAY 1 /* autoboot after 3 seconds */
+#define CONFIG_BOOTCOUNT_LIMIT 1
#undef CONFIG_BOOTARGS
@@ -57,6 +58,8 @@
"run ramargs addip addcon usbargs;" \
"bootm 200000 300000"
#define CFG_USB_ARGS "setenv bootargs $(bootargs) usbboot=1"
+#define CFG_BOOTLIMIT "3"
+#define CFG_ALT_BOOTCOMMAND "run usb_self;reset"
#define CONFIG_EXTRA_ENV_SETTINGS \
"hostname=abg405\0" \
@@ -88,8 +91,10 @@
"usb_load="CFG_USB_LOAD_COMMAND"\0" \
"usb_self="CFG_USB_SELF_COMMAND"\0" \
"usbargs="CFG_USB_ARGS"\0" \
+ "bootlimit="CFG_BOOTLIMIT"\0" \
+ "altbootcmd="CFG_ALT_BOOTCOMMAND"\0" \
""
-#define CONFIG_BOOTCOMMAND "run flash_self;run usb_self"
+#define CONFIG_BOOTCOMMAND "run flash_self;reset"
#define CONFIG_ETHADDR 00:02:27:8e:00:00
@@ -414,7 +419,12 @@ extern int flash_banks;
#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
#define CFG_GBL_DATA_SIZE 128 /* reserved bytes for initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+/* reserve some memory for BOOT limit info */
+#define CFG_INIT_SP_OFFSET (CFG_GBL_DATA_OFFSET - 16)
+
+#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
+#define CFG_BOOTCOUNT_ADDR (CFG_GBL_DATA_OFFSET - 8)
+#endif
/*
* Internal Definitions