MLK-11101 imx: mx6: Move the set_wdog_reset out of CONFIG_LDO_BYPASS_CHECK

Since the 6ul does not enable the CONFIG_LDO_BYPASS_CHECK, but have
to use the set_wdog_reset function. Need to move the funciton out of
CONFIG_LDO_BYPASS_CHECK to resolve build issue.

Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 9ea395d7ea6b8ed65d7d68a92d9832264872b447)

1 files changed, 22 insertions, 22 deletions

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 3f4b094..812594b 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -762,6 +762,28 @@ void s_init(void)
 	writel(mask528, &anatop->pfd_528_clr);
 }
 
+void set_wdog_reset(struct wdog_regs *wdog)
+{
+	u32 reg = readw(&wdog->wcr);
+	/*
+	 * use WDOG_B mode to reset external pmic because it's risky for the
+	 * following watchdog reboot in case of cpu freq at lowest 400Mhz with
+	 * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So
+	 * in ldo-bypass mode watchdog reset will only triger POR reset, not
+	 * WDOG reset. But below code depends on hardware design, if HW didn't
+	 * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip
+	 * these code since it assumed boot from 400Mhz always.
+	 */
+	reg = readw(&wdog->wcr);
+	reg |= 1 << 3;
+	/*
+	 * WDZST bit is write-once only bit. Align this bit in kernel,
+	 * otherwise kernel code will have no chance to set this bit.
+	 */
+	reg |= 1 << 0;
+	writew(reg, &wdog->wcr);
+}
+
 #ifdef CONFIG_LDO_BYPASS_CHECK
 DECLARE_GLOBAL_DATA_PTR;
 static int ldo_bypass;
@@ -854,28 +876,6 @@ void prep_anatop_bypass(void)
 #endif
 }
 
-void set_wdog_reset(struct wdog_regs *wdog)
-{
-	u32 reg = readw(&wdog->wcr);
-	/*
-	 * use WDOG_B mode to reset external pmic because it's risky for the
-	 * following watchdog reboot in case of cpu freq at lowest 400Mhz with
-	 * ldo-bypass mode. Because boot frequency maybe higher 800Mhz i.e. So
-	 * in ldo-bypass mode watchdog reset will only triger POR reset, not
-	 * WDOG reset. But below code depends on hardware design, if HW didn't
-	 * connect WDOG_B pin to external pmic such as i.mx6slevk, we can skip
-	 * these code since it assumed boot from 400Mhz always.
-	 */
-	reg = readw(&wdog->wcr);
-	reg |= 1 << 3;
-	/*
-	 * WDZST bit is write-once only bit. Align this bit in kernel,
-	 * otherwise kernel code will have no chance to set this bit.
-	 */
-	reg |= 1 << 0;
-	writew(reg, &wdog->wcr);
-}
-
 int set_anatop_bypass(int wdog_reset_pin)
 {
 	struct anatop_regs *anatop= (struct anatop_regs*)ANATOP_BASE_ADDR;