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| author | Leo Yan <leoy@marvell.com> | 2014-03-31 09:50:35 +0800 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-04-07 22:27:22 +0200 |
| commit | 42ddfad6ab6ad64d1c96a90636c36794284669b3 (patch) | |
| tree | 7aba3ec6c539ce781b3f4e0ccdf6ef9d02ebfd5d | |
| parent | 88590148fa8b7e2d7ca910a7a03b5c5700af58e4 (diff) | |
| download | u-boot-imx-42ddfad6ab6ad64d1c96a90636c36794284669b3.zip u-boot-imx-42ddfad6ab6ad64d1c96a90636c36794284669b3.tar.gz u-boot-imx-42ddfad6ab6ad64d1c96a90636c36794284669b3.tar.bz2 | |
ARMv8: fix bug for flush data cache by set/way
When flush the d$ with set/way instruction, it need calculate the way's
offset = log2(Associativity); but in current uboot's code, it use below
formula to calculate the offset: log2(Associativity * 2 - 1), so finally
it cannot flush data cache properly.
Signed-off-by: Leo Yan <leoy@marvell.com>
| -rw-r--r-- | arch/arm/cpu/armv8/cache.S | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/arm/cpu/armv8/cache.S b/arch/arm/cpu/armv8/cache.S index 249799c..4b3ee6e 100644 --- a/arch/arm/cpu/armv8/cache.S +++ b/arch/arm/cpu/armv8/cache.S @@ -31,9 +31,7 @@ ENTRY(__asm_flush_dcache_level) add x2, x2, #4 /* x2 <- log2(cache line size) */ mov x3, #0x3ff and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ - add w4, w3, w3 - sub w4, w4, 1 /* round up log2(#ways + 1) */ - clz w5, w4 /* bit position of #ways */ + clz w5, w3 /* bit position of #ways */ mov x4, #0x7fff and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ /* x12 <- cache level << 1 */ |