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| author | Ilya Ledvich <ilya@compulab.co.il> | 2013-06-17 16:59:27 +0300 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2013-07-02 09:21:16 -0400 |
| commit | 58c86c7d1d8f1bde92211068f2a8a97779c48e99 (patch) | |
| tree | 9467b18b3e8b77efce64de0339dbf6e083b70a6c | |
| parent | b0857c45c1f535069acf90e671b5e4b6cf662caf (diff) | |
| download | u-boot-imx-58c86c7d1d8f1bde92211068f2a8a97779c48e99.zip u-boot-imx-58c86c7d1d8f1bde92211068f2a8a97779c48e99.tar.gz u-boot-imx-58c86c7d1d8f1bde92211068f2a8a97779c48e99.tar.bz2 | |
am33xx: fix the ddr_cmdtctrl structure
Fix the wrong mapping between the DDR I/O control registers on AM33XX
SoCs and the software representation in the SPL code.
The most recent public TRM defines the following DDR I/O control registers
offsets:
* ddr_cmd0_ioctrl : offset 0x44E11404
* ddr_cmd1_ioctrl : offset 0x44E11408
* ddr_cmd2_ioctrl : offset 0x44E1140C
* ddr_data0_ioctrl: offset 0x44E11440
* ddr_data1_ioctrl: offset 0x44E11444
While the struct ddr_cmdtctrl has also some reserved bits in the beginning.
The struct is mapped to the address 0x44E11404. As a result "cm0ioctl" points
to the ddr_cmd1_ioctrl register, "cm1ioctl" to the ddr_cmd2_ioctrl and etc.
Registers ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because
of this mapping mismatch.
Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/ddr_defs.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index bb53a6a..d2f3a78 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -284,7 +284,6 @@ void config_ddr_data(const struct ddr_data *data, int nr); * This structure represents the DDR io control on AM33XX devices. */ struct ddr_cmdtctrl { - unsigned int resv1[1]; unsigned int cm0ioctl; unsigned int cm1ioctl; unsigned int cm2ioctl; |