ARM: tegra: pinmux: handle feature removal on newer SoCs

On some future SoCs, some of the per-drive-group features no longer
exist. Add some ifdefs to support this.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

5 files changed, 45 insertions, 0 deletions

diff --git a/arch/arm/include/asm/arch-tegra/pinmux.h b/arch/arm/include/asm/arch-tegra/pinmux.h
index c95c973..cb61aa1 100644
--- a/arch/arm/include/asm/arch-tegra/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra/pinmux.h
@@ -142,6 +142,7 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 #define PMUX_DRVDN_MAX	127
 #define PMUX_DRVDN_NONE	-1
 
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 /* Defines a pin group cfg's low-power mode select */
 enum pmux_lpmd {
 	PMUX_LPMD_X8 = 0,
@@ -150,20 +151,25 @@ enum pmux_lpmd {
 	PMUX_LPMD_X,
 	PMUX_LPMD_NONE = -1,
 };
+#endif
 
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 /* Defines whether a pin group cfg's schmidt is enabled or not */
 enum pmux_schmt {
 	PMUX_SCHMT_DISABLE = 0,
 	PMUX_SCHMT_ENABLE = 1,
 	PMUX_SCHMT_NONE = -1,
 };
+#endif
 
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
 enum pmux_hsm {
 	PMUX_HSM_DISABLE = 0,
 	PMUX_HSM_ENABLE = 1,
 	PMUX_HSM_NONE = -1,
 };
+#endif
 
 /*
  * This defines the configuration for a pin group's pad control config
@@ -174,9 +180,15 @@ struct pmux_drvgrp_config {
 	u32 slwr:3;		/* rising edge slew          */
 	u32 drvup:8;		/* pull-up drive strength    */
 	u32 drvdn:8;		/* pull-down drive strength  */
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 	u32 lpmd:3;		/* low-power mode selection  */
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 	u32 schmt:2;		/* schmidt enable            */
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
 	u32 hsm:2;		/* high-speed mode enable    */
+#endif
 };
 
 /**
diff --git a/arch/arm/include/asm/arch-tegra114/pinmux.h b/arch/arm/include/asm/arch-tegra114/pinmux.h
index 06a7572..4848c95 100644
--- a/arch/arm/include/asm/arch-tegra114/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra114/pinmux.h
@@ -315,6 +315,9 @@ enum pmux_func {
 
 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING
 #define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_GRPS_HAVE_LPMD
+#define TEGRA_PMX_GRPS_HAVE_SCHMT
+#define TEGRA_PMX_GRPS_HAVE_HSM
 #define TEGRA_PMX_PINS_HAVE_E_INPUT
 #define TEGRA_PMX_PINS_HAVE_LOCK
 #define TEGRA_PMX_PINS_HAVE_OD
diff --git a/arch/arm/include/asm/arch-tegra124/pinmux.h b/arch/arm/include/asm/arch-tegra124/pinmux.h
index c440f9f..4e6b88e 100644
--- a/arch/arm/include/asm/arch-tegra124/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra124/pinmux.h
@@ -337,6 +337,9 @@ enum pmux_func {
 
 #define TEGRA_PMX_SOC_HAS_IO_CLAMPING
 #define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_GRPS_HAVE_LPMD
+#define TEGRA_PMX_GRPS_HAVE_SCHMT
+#define TEGRA_PMX_GRPS_HAVE_HSM
 #define TEGRA_PMX_PINS_HAVE_E_INPUT
 #define TEGRA_PMX_PINS_HAVE_LOCK
 #define TEGRA_PMX_PINS_HAVE_OD
diff --git a/arch/arm/include/asm/arch-tegra30/pinmux.h b/arch/arm/include/asm/arch-tegra30/pinmux.h
index e9046ff..56117a4 100644
--- a/arch/arm/include/asm/arch-tegra30/pinmux.h
+++ b/arch/arm/include/asm/arch-tegra30/pinmux.h
@@ -392,6 +392,9 @@ enum pmux_func {
 };
 
 #define TEGRA_PMX_SOC_HAS_DRVGRPS
+#define TEGRA_PMX_GRPS_HAVE_LPMD
+#define TEGRA_PMX_GRPS_HAVE_SCHMT
+#define TEGRA_PMX_GRPS_HAVE_HSM
 #define TEGRA_PMX_PINS_HAVE_E_INPUT
 #define TEGRA_PMX_PINS_HAVE_LOCK
 #define TEGRA_PMX_PINS_HAVE_OD
diff --git a/arch/arm/mach-tegra/pinmux-common.c b/arch/arm/mach-tegra/pinmux-common.c
index 5d4d2e9..f24e8c4 100644
--- a/arch/arm/mach-tegra/pinmux-common.c
+++ b/arch/arm/mach-tegra/pinmux-common.c
@@ -352,19 +352,31 @@ void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
 #define pmux_drv_isvalid(drv) \
 	(((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
 
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 #define pmux_lpmd_isvalid(lpm) \
 	(((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
+#endif
 
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 #define pmux_schmt_isvalid(schmt) \
 	(((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
+#endif
 
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
 #define pmux_hsm_isvalid(hsm) \
 	(((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
+#endif
 
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
 #define HSM_SHIFT	2
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 #define SCHMT_SHIFT	3
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 #define LPMD_SHIFT	4
 #define LPMD_MASK	(3 << LPMD_SHIFT)
+#endif
 /*
  * Note that the following DRV* and SLW* defines are accurate for many drive
  * groups on many SoCs. We really need a per-group data structure to solve
@@ -473,6 +485,7 @@ static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
 	return;
 }
 
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
 {
 	u32 *reg = DRV_REG(grp);
@@ -493,7 +506,9 @@ static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
 
 	return;
 }
+#endif
 
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
 {
 	u32 *reg = DRV_REG(grp);
@@ -516,7 +531,9 @@ static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
 
 	return;
 }
+#endif
 
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
 {
 	u32 *reg = DRV_REG(grp);
@@ -539,6 +556,7 @@ static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
 
 	return;
 }
+#endif
 
 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
 {
@@ -548,9 +566,15 @@ static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
 	pinmux_set_drvdn_slwr(grp, config->slwr);
 	pinmux_set_drvup(grp, config->drvup);
 	pinmux_set_drvdn(grp, config->drvdn);
+#ifdef TEGRA_PMX_GRPS_HAVE_LPMD
 	pinmux_set_lpmd(grp, config->lpmd);
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
 	pinmux_set_schmt(grp, config->schmt);
+#endif
+#ifdef TEGRA_PMX_GRPS_HAVE_HSM
 	pinmux_set_hsm(grp, config->hsm);
+#endif
 }
 
 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,