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| author | Lokesh Vutla <lokeshvutla@ti.com> | 2014-06-02 10:49:03 +0530 |
|---|---|---|
| committer | Tom Rini <trini@ti.com> | 2014-06-06 17:46:15 -0400 |
| commit | ccd2f8db814b88bf4f7a7d418048051d259014a4 (patch) | |
| tree | fca96e748394fad035cfd12a2caf04b743762c9e | |
| parent | fa03834fdf62eb40bc2d47c0e4289d6c250cb148 (diff) | |
| download | u-boot-imx-ccd2f8db814b88bf4f7a7d418048051d259014a4.zip u-boot-imx-ccd2f8db814b88bf4f7a7d418048051d259014a4.tar.gz u-boot-imx-ccd2f8db814b88bf4f7a7d418048051d259014a4.tar.bz2 | |
ARM: AM43xx: Fix UART clocks enabling
After enabling a module, SW has to wait on IDLEST bit
until it is Fully functional. This wait is missing for UART module
and there is a immediate access of UART registers after this. So there
is a chance of hang on this module( This can happen when we are running
from MPU SRAM). So waiting for IDLEST bit.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/clock_am43xx.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c index d0bc234..31188c8 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c @@ -53,6 +53,8 @@ const struct dpll_regs dpll_ddr_regs = { void setup_clocks_for_console(void) { + u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED; + /* Do not add any spl_debug prints in this function */ clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK, CD_CLKCTRL_CLKTRCTRL_SW_WKUP << @@ -63,6 +65,13 @@ void setup_clocks_for_console(void) MODULE_CLKCTRL_MODULEMODE_MASK, MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN << MODULE_CLKCTRL_MODULEMODE_SHIFT); + + while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) || + (idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) { + clkctrl = readl(&cmwkup->wkup_uart0ctrl); + idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >> + MODULE_CLKCTRL_IDLEST_SHIFT; + } } void enable_basic_clocks(void) |