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| author | Kumar Gala <galak@kernel.crashing.org> | 2009-09-22 15:45:44 -0500 |
|---|---|---|
| committer | Tom Rix <Tom.Rix@windriver.com> | 2009-10-03 09:04:38 -0500 |
| commit | fd8dfa17e9a0f360414523ab441e132fa65538d7 (patch) | |
| tree | 89d48d914e27e7ae925766d783f7b5ee8ed77675 | |
| parent | b5190df365255ddc77a2f48ec14ed9c07c34129e (diff) | |
| download | u-boot-imx-fd8dfa17e9a0f360414523ab441e132fa65538d7.zip u-boot-imx-fd8dfa17e9a0f360414523ab441e132fa65538d7.tar.gz u-boot-imx-fd8dfa17e9a0f360414523ab441e132fa65538d7.tar.bz2 | |
ppc/85xx: Fix enabling of L2 cache
We need to flash invalidate the locks in addition to the cache
before we enable.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | cpu/mpc85xx/cpu_init.c | 4 | ||||
| -rw-r--r-- | cpu/mpc85xx/release.S | 3 |
2 files changed, 4 insertions, 3 deletions
diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index a6d1e99..a8d83b1 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -336,8 +336,8 @@ int cpu_init_r(void) u32 l2cfg0 = mfspr(SPRN_L2CFG0); /* invalidate the L2 cache */ - mtspr(SPRN_L2CSR0, L2CSR0_L2FI); - while (mfspr(SPRN_L2CSR0) & L2CSR0_L2FI) + mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC)); + while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) ; /* enable the cache */ diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index 074b056..ecbd0d5 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -102,7 +102,8 @@ __secondary_start_page: #ifdef CONFIG_BACKSIDE_L2_CACHE /* Enable/invalidate the L2 cache */ msync - lis r3,L2CSR0_L2FI@h + lis r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h + ori r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l mtspr SPRN_L2CSR0,r3 1: mfspr r3,SPRN_L2CSR0 |