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authorMarkus Klotzbuecher <mk@denx.de>2006-03-29 17:59:20 +0200
committerMarkus Klotzbücher <mk@pollux.denx.de>2006-03-29 17:59:20 +0200
commiteeaab720f66f0281b9a1ea3c1f8765bf34e4411e (patch)
treeece6d1464597fa52a327e1f4eb16bb61dbc0666c
parent89f2dfa4c349ae3b040779ac0ab1c9baa1ef025d (diff)
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Change delta board memory map to start at 0x80000000.
-rw-r--r--board/delta/config.mk2
-rw-r--r--include/configs/delta.h14
2 files changed, 8 insertions, 8 deletions
diff --git a/board/delta/config.mk b/board/delta/config.mk
index 9564625..c72e956 100644
--- a/board/delta/config.mk
+++ b/board/delta/config.mk
@@ -2,7 +2,7 @@
#TEXT_BASE = 0xa1700000
#TEXT_BASE = 0xa3080000
#TEXT_BASE = 0x9ffe0000
-TEXT_BASE = 0xa3008000
+TEXT_BASE = 0x83008000
# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE)
BOARDLIBS = drivers/nand/libnand.a
diff --git a/include/configs/delta.h b/include/configs/delta.h
index f2e0a8c..053a8f7 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -125,8 +125,8 @@
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#define CFG_DEVICE_NULLDEV 1
-#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
-#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
+#define CFG_MEMTEST_START 0x80400000 /* memtest works on */
+#define CFG_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */
#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
@@ -159,16 +159,16 @@
* Physical Memory Map
*/
#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
-#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */
-#define PHYS_SDRAM_2 0xa1000000 /* SDRAM Bank #2 */
+#define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */
#define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */
-#define PHYS_SDRAM_3 0xa2000000 /* SDRAM Bank #3 */
+#define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */
#define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */
-#define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */
+#define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */
#define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */
-#define CFG_DRAM_BASE 0xa0000000 /* at CS0 */
+#define CFG_DRAM_BASE 0x80000000 /* at CS0 */
#define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */
#undef CFG_SKIP_DRAM_SCRUB