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authorStefan Roese <sr@denx.de>2007-02-20 13:17:42 +0100
committerStefan Roese <sr@denx.de>2007-02-20 13:17:42 +0100
commitd93e2212f962668b3dce091ff5edc33f2347fe37 (patch)
tree19b9b366ae1bdb33437370fa5dd009068c2039ec
parent874bb7b88fe9b4648e1288a387af2e31014a72f3 (diff)
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[PATCH] Update SystemACE driver for 16bit access
This patch removes some problems when the Xilinx SystemACE driver is used with 16bit access on an big endian platform (like the AMCC Katmai). Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r--drivers/systemace.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/systemace.c b/drivers/systemace.c
index 9502623..3bd2ea9 100644
--- a/drivers/systemace.c
+++ b/drivers/systemace.c
@@ -66,8 +66,8 @@
writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);}
#endif
#else
-#define ace_readw(off) (readw(CFG_SYSTEMACE_BASE+off))
-#define ace_writew(val, off) (writew(val, CFG_SYSTEMACE_BASE+off))
+#define ace_readw(off) (in16(CFG_SYSTEMACE_BASE+off))
+#define ace_writew(val, off) (out16(CFG_SYSTEMACE_BASE+off,val))
#endif
/* */
@@ -119,6 +119,14 @@ block_dev_desc_t *systemace_get_dev(int dev)
systemace_dev.removable = 1;
systemace_dev.block_read = systemace_read;
+#if (CFG_SYSTEMACE_WIDTH == 16)
+ /*
+ * By default the SystemACE comes up in 8-bit mode.
+ * Ensure that 16-bit mode gets enabled.
+ */
+ ace_writew(0x0001, 0);
+#endif
+
init_part(&systemace_dev);
}
@@ -197,7 +205,7 @@ static unsigned long systemace_read(int dev, unsigned long start,
#endif
/* Write LBA block address */
ace_writew((start >> 0) & 0xffff, 0x10);
- ace_writew((start >> 16) & 0x00ff, 0x12);
+ ace_writew((start >> 16) & 0x0fff, 0x12);
/* NOTE: in the Write Sector count below, a count of 0
causes a transfer of 256, so &0xff gives the right