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| author | Tom Rini <trini@ti.com> | 2012-07-24 14:03:24 -0700 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2012-09-01 14:58:12 +0200 |
| commit | c48c89543310bae633c7aa44a0fc94b9c97c8453 (patch) | |
| tree | e264c85efcbb9487b82389995a3f62ac03cf5c0d | |
| parent | 7d8a961d31965799b5ede64e0992232e04c2d009 (diff) | |
| download | u-boot-imx-c48c89543310bae633c7aa44a0fc94b9c97c8453.zip u-boot-imx-c48c89543310bae633c7aa44a0fc94b9c97c8453.tar.gz u-boot-imx-c48c89543310bae633c7aa44a0fc94b9c97c8453.tar.bz2 | |
am33xx: Document what we're doing with ddrctrl->ddrckectrl
- Remove the call to set ddrctrl->ddrioctrl as it's all zeros.
- Comment what we're really setting in ddrctrl->ddrckectrl which is that
we're operating in the normal mode where EMIF/PHY clock is controlled
by the PHY.
Signed-off-by: Tom Rini <trini@ti.com>
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/emif4.c | 6 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-am33xx/ddr_defs.h | 1 |
2 files changed, 3 insertions, 4 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/emif4.c b/arch/arm/cpu/armv7/am33xx/emif4.c index 684b123..e04e970 100644 --- a/arch/arm/cpu/armv7/am33xx/emif4.c +++ b/arch/arm/cpu/armv7/am33xx/emif4.c @@ -170,10 +170,8 @@ void config_ddr(short ddr_type) config_io_ctrl(&ioctrl); - writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, - &ddrctrl->ddrioctrl); - writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, - &ddrctrl->ddrckectrl); + /* Set CKE to be controlled by EMIF/DDR PHY */ + writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); config_emif_ddr2(); } diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 879c5fb..f755736 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -28,6 +28,7 @@ #define CMD_FORCE 0x00 #define CMD_DELAY 0x00 #define PHY_DLL_LOCK_DIFF 0x0 +#define DDR_CKE_CTRL_NORMAL 0x1 #define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */ #define DDR2_EMIF_TIM1 0x0666B3C9 |