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authorFranck Jullien <franck.jullien@gmail.com>2014-05-21 22:43:49 +0200
committerTom Rini <trini@ti.com>2014-06-05 14:44:56 -0400
commitc346cf13509c9bfcd98c679a9822bb346432b9b6 (patch)
treee780e1d48bde6ffeef1aae67acffb2e76a0c66d3
parent08be2836df0b07aac65fea583b762335569fd47a (diff)
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openrisc: update SPR registers definition
The OpenRISC architecture specification v1.0 defines new SPR registers. This patch adds registers definition for group 0 and update bit definitions for the CPU configuration register. Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
-rw-r--r--arch/openrisc/include/asm/spr-defs.h13
1 files changed, 12 insertions, 1 deletions
diff --git a/arch/openrisc/include/asm/spr-defs.h b/arch/openrisc/include/asm/spr-defs.h
index a863b3e..e30d210 100644
--- a/arch/openrisc/include/asm/spr-defs.h
+++ b/arch/openrisc/include/asm/spr-defs.h
@@ -46,6 +46,11 @@
#define SPR_ICCFGR (SPRGROUP_SYS + 6)
#define SPR_DCFGR (SPRGROUP_SYS + 7)
#define SPR_PCCFGR (SPRGROUP_SYS + 8)
+#define SPR_VR2 (SPRGROUP_SYS + 9)
+#define SPR_AVR (SPRGROUP_SYS + 10)
+#define SPR_EVBAR (SPRGROUP_SYS + 11)
+#define SPR_AECR (SPRGROUP_SYS + 12)
+#define SPR_AESR (SPRGROUP_SYS + 13)
#define SPR_NPC (SPRGROUP_SYS + 16)
#define SPR_SR (SPRGROUP_SYS + 17)
#define SPR_PPC (SPRGROUP_SYS + 18)
@@ -161,7 +166,13 @@
#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
-#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */
+#define SPR_CPUCFGR_ND 0x00000400 /* No delay slot */
+#define SPR_CPUCFGR_AVRP 0x00000800 /* Arch. Version Register present */
+#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception Vector Base Address Register (EVBAR) present */
+#define SPR_CPUCFGR_ISRP 0x00002000 /* Implementation-Specific Registers (ISR0-7) present */
+#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic Exception Control Register (AECR) and */
+ /* Arithmetic Exception Status Register (AESR) presents */
+#define SPR_CPUCFGR_RES 0xffffc000 /* Reserved */
/*
* Bit definitions for the Debug configuration register and other