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authorDipen Dudhat <Dipen.Dudhat@freescale.com>2011-01-19 12:46:27 +0530
committerKumar Gala <galak@kernel.crashing.org>2011-01-19 22:58:24 -0600
commitbeba93ed05d8cea795bad895b6cc1490004fc242 (patch)
tree43f6f94012a276a1e69c27e47c34d4b449a3173e
parentb7070904327d10eb789ccafa4622659ffaa6645c (diff)
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powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBC
Future SoC (like the P1010) replace the LBC controller with the new IFC (Integrated Flash Controller) so ensure we properly protect code that is related to the LBC. Signed-off-by: Dipen Dudhat <Dipen.Dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c9
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c6
2 files changed, 13 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 4ef9be1..1aad2ba 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
* (C) Copyright 2002, 2003 Motorola Inc.
* Xianghua Xiao (X.Xiao@motorola.com)
*
@@ -166,12 +166,14 @@ int checkcpu (void)
}
#endif
+#if defined(CONFIG_FSL_LBC)
if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
} else {
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
sysinfo.freqLocalBus);
}
+#endif
#ifdef CONFIG_CPM2
printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
@@ -284,7 +286,10 @@ void mpc85xx_reginfo(void)
{
print_tlbcam();
print_laws();
+#if defined(CONFIG_FSL_LBC)
print_lbc_regs();
+#endif
+
}
/* Common ddr init for non-corenet fsl 85xx platforms */
@@ -330,8 +335,10 @@ phys_size_t initdram(int board_type)
ddr_enable_ecc(dram_size);
#endif
+#if defined(CONFIG_FSL_LBC)
/* Some boards also have sdram on the lbc */
lbc_sdram_init();
+#endif
puts("DDR: ");
return dram_size;
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index dd4c6b3..f2aa8d0 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
*
* (C) Copyright 2003 Motorola Inc.
* Xianghua Xiao, (X.Xiao@motorola.com)
@@ -131,7 +131,9 @@ void get_sys_info (sys_info_t * sysInfo)
#else
uint plat_ratio,e500_ratio,half_freqSystemBus;
+#if defined(CONFIG_FSL_LBC)
uint lcrr_div;
+#endif
int i;
#ifdef CONFIG_QE
u32 qe_ratio;
@@ -168,6 +170,7 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
#endif
+#if defined(CONFIG_FSL_LBC)
#if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
@@ -193,6 +196,7 @@ void get_sys_info (sys_info_t * sysInfo)
/* In case anyone cares what the unknown value is */
sysInfo->freqLocalBus = lcrr_div;
}
+#endif
}