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authorWolfgang Denk <wd@denx.de>2008-08-25 23:34:22 +0200
committerWolfgang Denk <wd@denx.de>2008-08-25 23:34:22 +0200
commitb97a31165ab042543bac38f692cf98575367afc4 (patch)
tree6fc13d6951d24728c29c4f45aa15c84a5e5d9578
parent4d56e8dea670757c801a6a65531f02a8f981ce1f (diff)
parent079edb913dbae147b50a488cf02e03f473fc5f28 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
-rw-r--r--cpu/arm1136/mx31/generic.c4
-rw-r--r--cpu/arm926ejs/davinci/nand.c5
-rwxr-xr-x[-rw-r--r--]cpu/arm926ejs/versatile/timer.c39
-rw-r--r--drivers/rtc/Makefile1
-rwxr-xr-xdrivers/rtc/pl031.c123
5 files changed, 162 insertions, 10 deletions
diff --git a/cpu/arm1136/mx31/generic.c b/cpu/arm1136/mx31/generic.c
index dc031c9..1415d6c 100644
--- a/cpu/arm1136/mx31/generic.c
+++ b/cpu/arm1136/mx31/generic.c
@@ -27,8 +27,8 @@
static u32 mx31_decode_pll(u32 reg, u32 infreq)
{
u32 mfi = (reg >> 10) & 0xf;
- u32 mfn = reg & 0x3f;
- u32 mfd = (reg >> 16) & 0x3f;
+ u32 mfn = reg & 0x3ff;
+ u32 mfd = (reg >> 16) & 0x3ff;
u32 pd = (reg >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c
index 2aa01d6..5a1da63 100644
--- a/cpu/arm926ejs/davinci/nand.c
+++ b/cpu/arm926ejs/davinci/nand.c
@@ -90,7 +90,6 @@ static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
#ifdef CFG_NAND_HW_ECC
#ifdef CFG_NAND_LARGEPAGE
static struct nand_ecclayout davinci_nand_ecclayout = {
- .useecc = MTD_NANDECC_AUTOPLACE,
.eccbytes = 12,
.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
.oobfree = {
@@ -103,7 +102,6 @@ static struct nand_ecclayout davinci_nand_ecclayout = {
};
#elif defined(CFG_NAND_SMALLPAGE)
static struct nand_ecclayout davinci_nand_ecclayout = {
- .useecc = MTD_NANDECC_AUTOPLACE,
.eccbytes = 3,
.eccpos = {0, 1, 2},
.oobfree = {
@@ -371,12 +369,11 @@ int board_nand_init(struct nand_chip *nand)
nand->options = NAND_USE_FLASH_BBT;
#endif
#ifdef CFG_NAND_HW_ECC
-#ifdef CFG_NAND_LARGEPAGE
nand->ecc.mode = NAND_ECC_HW;
+#ifdef CFG_NAND_LARGEPAGE
nand->ecc.size = 2048;
nand->ecc.bytes = 12;
#elif defined(CFG_NAND_SMALLPAGE)
- nand->ecc.mode = NAND_ECC_HW;
nand->ecc.size = 512;
nand->ecc.bytes = 3;
#else
diff --git a/cpu/arm926ejs/versatile/timer.c b/cpu/arm926ejs/versatile/timer.c
index 32872d2..f01f318 100644..100755
--- a/cpu/arm926ejs/versatile/timer.c
+++ b/cpu/arm926ejs/versatile/timer.c
@@ -46,12 +46,43 @@
static ulong timestamp;
static ulong lastdec;
-/* nothing really to do with interrupts, just starts up a counter. */
+#define TIMER_ENABLE (1 << 7)
+#define TIMER_MODE_MSK (1 << 6)
+#define TIMER_MODE_FR (0 << 6)
+#define TIMER_MODE_PD (1 << 6)
+
+#define TIMER_INT_EN (1 << 5)
+#define TIMER_PRS_MSK (3 << 2)
+#define TIMER_PRS_8S (1 << 3)
+#define TIMER_SIZE_MSK (1 << 2)
+#define TIMER_ONE_SHT (1 << 0)
+
int timer_init (void)
{
- *(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD; /* TimerLoad */
- *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD; /* TimerValue */
- *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C;
+ ulong tmr_ctrl_val;
+
+ /* 1st disable the Timer */
+ tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8);
+ tmr_ctrl_val &= ~TIMER_ENABLE;
+ *(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val;
+
+ /*
+ * The Timer Control Register has one Undefined/Shouldn't Use Bit
+ * So we should do read/modify/write Operation
+ */
+
+ /*
+ * Timer Mode : Free Running
+ * Interrupt : Disabled
+ * Prescale : 8 Stage, Clk/256
+ * Tmr Siz : 16 Bit Counter
+ * Tmr in Wrapping Mode
+ */
+ tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8);
+ tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
+ tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
+
+ *(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val;
/* init the timestamp and lastdec value */
reset_timer_masked();
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 86f855f..f41f33d 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -53,6 +53,7 @@ COBJS-$(CONFIG_RTC_MK48T59) += mk48t59.o
COBJS-$(CONFIG_RTC_MPC5200) += mpc5xxx.o
COBJS-$(CONFIG_RTC_MPC8xx) += mpc8xx.o
COBJS-$(CONFIG_RTC_PCF8563) += pcf8563.o
+COBJS-$(CONFIG_RTC_PL031) += pl031.o
COBJS-$(CONFIG_RTC_RS5C372A) += rs5c372.o
COBJS-$(CONFIG_RTC_RX8025) += rx8025.o
COBJS-$(CONFIG_RTC_S3C24X0) += s3c24x0_rtc.o
diff --git a/drivers/rtc/pl031.c b/drivers/rtc/pl031.c
new file mode 100755
index 0000000..276c184
--- /dev/null
+++ b/drivers/rtc/pl031.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2008
+ * Gururaja Hebbar gururajakr@sanyo.co.in
+ *
+ * reference linux-2.6.20.6/drivers/rtc/rtc-pl031.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <rtc.h>
+
+#if defined(CONFIG_CMD_DATE)
+
+#ifndef CFG_RTC_PL031_BASE
+#error CFG_RTC_PL031_BASE is not defined!
+#endif
+
+/*
+ * Register definitions
+ */
+#define RTC_DR 0x00 /* Data read register */
+#define RTC_MR 0x04 /* Match register */
+#define RTC_LR 0x08 /* Data load register */
+#define RTC_CR 0x0c /* Control register */
+#define RTC_IMSC 0x10 /* Interrupt mask and set register */
+#define RTC_RIS 0x14 /* Raw interrupt status register */
+#define RTC_MIS 0x18 /* Masked interrupt status register */
+#define RTC_ICR 0x1c /* Interrupt clear register */
+
+#define RTC_CR_START (1 << 0)
+
+#define RTC_WRITE_REG(addr, val) \
+ (*(volatile unsigned int *)(CFG_RTC_PL031_BASE + (addr)) = (val))
+#define RTC_READ_REG(addr) \
+ (*(volatile unsigned int *)(CFG_RTC_PL031_BASE + (addr)))
+
+static int pl031_initted = 0;
+
+/* Enable RTC Start in Control register*/
+void rtc_init(void)
+{
+ RTC_WRITE_REG(RTC_CR, RTC_CR_START);
+
+ pl031_initted = 1;
+}
+
+/*
+ * Reset the RTC. We set the date back to 1970-01-01.
+ */
+void rtc_reset(void)
+{
+ RTC_WRITE_REG(RTC_LR, 0x00);
+ if(!pl031_initted)
+ rtc_init();
+}
+
+/*
+ * Set the RTC
+*/
+void rtc_set(struct rtc_time *tmp)
+{
+ unsigned long tim;
+
+ if(!pl031_initted)
+ rtc_init();
+
+ if (tmp == NULL) {
+ puts("Error setting the date/time\n");
+ return;
+ }
+
+ /* Calculate number of seconds this incoming time represents */
+ tim = mktime(tmp->tm_year, tmp->tm_mon, tmp->tm_mday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ RTC_WRITE_REG(RTC_LR, tim);
+}
+
+/*
+ * Get the current time from the RTC
+ */
+int rtc_get(struct rtc_time *tmp)
+{
+ ulong tim;
+
+ if(!pl031_initted)
+ rtc_init();
+
+ if (tmp == NULL) {
+ puts("Error getting the date/time\n");
+ return -1;
+ }
+
+ tim = RTC_READ_REG(RTC_DR);
+
+ to_tm (tim, tmp);
+
+ debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+
+ return 0;
+}
+
+#endif