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authorHaiying Wang <Haiying.Wang@freescale.com>2010-09-29 13:31:36 -0400
committerKumar Gala <galak@kernel.crashing.org>2010-10-07 09:49:47 -0500
commitb6bde930901b1375264865b979507eb25806cb77 (patch)
tree036cd7c39a9d11753fb1cdc27b54672ec239c5c5
parent3aed55074211b4e886d97f16773f186a019d508d (diff)
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mpc8569mds: fix some ddr settings
Enable half drive strength, set RTT to 60Ohm and set write leveling override. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--board/freescale/mpc8569mds/ddr.c16
1 files changed, 13 insertions, 3 deletions
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
index e938788..e3f5b4a 100644
--- a/board/freescale/mpc8569mds/ddr.c
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -77,8 +77,18 @@ void fsl_ddr_board_options(memctl_options_t *popts,
popts->write_data_delay = 2;
/*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
+ * Enable half drive strength
*/
- popts->half_strength_driver_enable = 0;
+ popts->half_strength_driver_enable = 1;
+
+ /* Write leveling override */
+ popts->wrlvl_en = 1;
+ popts->wrlvl_override = 1;
+ popts->wrlvl_sample = 0xa;
+ popts->wrlvl_start = 0x4;
+
+ /* Rtt and Rtt_W override */
+ popts->rtt_override = 1;
+ popts->rtt_override_value = DDR3_RTT_60_OHM;
+ popts->rtt_wr_override_value = 0; /* Rtt_WR= dynamic ODT off */
}