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authorBin Meng <bmeng.cn@gmail.com>2015-02-05 23:42:27 +0800
committerSimon Glass <sjg@chromium.org>2015-02-06 12:07:44 -0700
commitb1420c813074d39cd2452d7bc45374561d1cf223 (patch)
tree975cde7f76f6b8c9087ca8e27b959913ca9d478b
parentc89ada017fe24891818c08a9e4b7c5ae4a9224e5 (diff)
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dt-bindings: Add Intel Quark MRC bindings
Add standard dt-bindings macros to be used by Intel Quark MRC node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
-rw-r--r--include/dt-bindings/mrc/quark.h83
1 files changed, 83 insertions, 0 deletions
diff --git a/include/dt-bindings/mrc/quark.h b/include/dt-bindings/mrc/quark.h
new file mode 100644
index 0000000..e3ca8a2
--- /dev/null
+++ b/include/dt-bindings/mrc/quark.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Intel Quark MRC bindings include several properties
+ * as part of an Intel Quark MRC node. In most cases,
+ * the value of these properties uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_QRK_MRC_H_
+#define _DT_BINDINGS_QRK_MRC_H_
+
+/* MRC platform data flags */
+#define MRC_FLAG_ECC_EN 0x00000001
+#define MRC_FLAG_SCRAMBLE_EN 0x00000002
+#define MRC_FLAG_MEMTEST_EN 0x00000004
+/* 0b DDR "fly-by" topology else 1b DDR "tree" topology */
+#define MRC_FLAG_TOP_TREE_EN 0x00000008
+/* If set ODR signal is asserted to DRAM devices on writes */
+#define MRC_FLAG_WR_ODT_EN 0x00000010
+
+/* DRAM width */
+#define DRAM_WIDTH_X8 0
+#define DRAM_WIDTH_X16 1
+#define DRAM_WIDTH_X32 2
+
+/* DRAM speed */
+#define DRAM_FREQ_800 0
+#define DRAM_FREQ_1066 1
+
+/* DRAM type */
+#define DRAM_TYPE_DDR3 0
+#define DRAM_TYPE_DDR3L 1
+
+/* DRAM rank mask */
+#define DRAM_RANK(n) (1 << (n))
+
+/* DRAM channel mask */
+#define DRAM_CHANNEL(n) (1 << (n))
+
+/* DRAM channel width */
+#define DRAM_CHANNEL_WIDTH_X8 0
+#define DRAM_CHANNEL_WIDTH_X16 1
+#define DRAM_CHANNEL_WIDTH_X32 2
+
+/* DRAM address mode */
+#define DRAM_ADDR_MODE0 0
+#define DRAM_ADDR_MODE1 1
+#define DRAM_ADDR_MODE2 2
+
+/* DRAM refresh rate */
+#define DRAM_REFRESH_RATE_195US 1
+#define DRAM_REFRESH_RATE_39US 2
+#define DRAM_REFRESH_RATE_785US 3
+
+/* DRAM SR temprature range */
+#define DRAM_SRT_RANGE_NORMAL 0
+#define DRAM_SRT_RANGE_EXTENDED 1
+
+/* DRAM ron value */
+#define DRAM_RON_34OHM 0
+#define DRAM_RON_40OHM 1
+
+/* DRAM rtt nom value */
+#define DRAM_RTT_NOM_40OHM 0
+#define DRAM_RTT_NOM_60OHM 1
+#define DRAM_RTT_NOM_120OHM 2
+
+/* DRAM rd odt value */
+#define DRAM_RD_ODT_OFF 0
+#define DRAM_RD_ODT_60OHM 1
+#define DRAM_RD_ODT_120OHM 2
+#define DRAM_RD_ODT_180OHM 3
+
+/* DRAM density */
+#define DRAM_DENSITY_512M 0
+#define DRAM_DENSITY_1G 1
+#define DRAM_DENSITY_2G 2
+#define DRAM_DENSITY_4G 3
+
+#endif /* _DT_BINDINGS_QRK_MRC_H_ */