powerpc: mpc5xxx: remove board support for MVBC_P and MVSMR

These boards have been orphaned for more than 6 months.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

26 files changed, 2 insertions, 1848 deletions

diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig
index cca58e5..8a477e7 100644
--- a/arch/powerpc/cpu/mpc5xxx/Kconfig
+++ b/arch/powerpc/cpu/mpc5xxx/Kconfig
@@ -97,12 +97,6 @@ config TARGET_MUCMC52
 config TARGET_UC101
 	bool "Support uc101"
 
-config TARGET_MVBC_P
-	bool "Support MVBC_P"
-
-config TARGET_MVSMR
-	bool "Support MVSMR"
-
 config TARGET_PCM030
 	bool "Support pcm030"
 
@@ -139,8 +133,6 @@ source "board/jupiter/Kconfig"
 source "board/manroland/hmi1001/Kconfig"
 source "board/manroland/mucmc52/Kconfig"
 source "board/manroland/uc101/Kconfig"
-source "board/matrix_vision/mvbc_p/Kconfig"
-source "board/matrix_vision/mvsmr/Kconfig"
 source "board/mcc200/Kconfig"
 source "board/motionpro/Kconfig"
 source "board/munices/Kconfig"
diff --git a/board/matrix_vision/mvbc_p/Kconfig b/board/matrix_vision/mvbc_p/Kconfig
deleted file mode 100644
index 4a68493..0000000
--- a/board/matrix_vision/mvbc_p/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MVBC_P
-
-config SYS_BOARD
-	default "mvbc_p"
-
-config SYS_VENDOR
-	default "matrix_vision"
-
-config SYS_CONFIG_NAME
-	default "MVBC_P"
-
-endif
diff --git a/board/matrix_vision/mvbc_p/MAINTAINERS b/board/matrix_vision/mvbc_p/MAINTAINERS
deleted file mode 100644
index aad14ed..0000000
--- a/board/matrix_vision/mvbc_p/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MVBC_P BOARD
-#M:	Andre Schwarz <andre.schwarz@matrix-vision.de>
-S:	Orphan (since 2014-03)
-F:	board/matrix_vision/mvbc_p/
-F:	include/configs/MVBC_P.h
-F:	configs/MVBC_P_defconfig
diff --git a/board/matrix_vision/mvbc_p/Makefile b/board/matrix_vision/mvbc_p/Makefile
deleted file mode 100644
index 4c19941..0000000
--- a/board/matrix_vision/mvbc_p/Makefile
+++ /dev/null
@@ -1,11 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004-2008
-# Matrix-Vision GmbH, info@matrix-vision.de
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mvbc_p.o fpga.o
diff --git a/board/matrix_vision/mvbc_p/README.mvbc_p b/board/matrix_vision/mvbc_p/README.mvbc_p
deleted file mode 100644
index a691137..0000000
--- a/board/matrix_vision/mvbc_p/README.mvbc_p
+++ /dev/null
@@ -1,73 +0,0 @@
-Matrix Vision mvBlueCOUGAR-P (mvBC-P)
--------------------------------------
-
-1.	Board Description
-
-	The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera
-	with main focus on GigEVision protocol in combination with local image
-	preprocessing.
-
-	Power Supply is either VDC 48V or Pover over Ethernet (PoE).
-
-2	System Components
-
-2.1	CPU
-	Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
-	64MB SDRAM @ 133MHz.
-	8 MByte Nor Flash on local bus.
-	1 serial ports. Console running on ttyS0 @ 115200 8N1.
-
-2.2	PCI
-	PCI clock fixed at 66MHz. Arbitration inside FPGA.
-	Intel GD82541ER network MAC/PHY and FPGA connected.
-
-2.3	FPGA
-	Altera Cyclone-II EP2C8 with PCI DMA engine.
-	Connects to Matrix Vision specific CCD/CMOS sensor interface.
-	Utilizes 64MB Nand Flash.
-
-2.3.1	I/O @ FPGA
-	2 Outputs : photo coupler
-	2 Inputs  : photo coupler
-
-2.4	I2C
-	LM75 @ 0x90 for temperature monitoring.
-	EEPROM @ 0xA0 for vendor specifics.
-	image sensor interface (slave addresses depend on sensor)
-
-3	Flash layout.
-
-	reset vector is 0x00000100, i.e. "LOWBOOT".
-
-	FF800000	u-boot
-	FF840000	u-boot script image
-	FF850000	redundant u-boot script image
-	FF860000	FPGA raw bit file
-	FF8A0000	tbd.
-	FF900000	root FS
-	FFC00000	kernel
-	FFFC0000	device tree blob
-	FFFD0000	redundant device tree blob
-	FFFE0000	environment
-	FFFF0000	redundant environment
-
-	mtd partitions are propagated to linux kernel via device tree blob.
-
-4	Booting
-
-	On startup the bootscript @ FF840000 is executed. This script can be
-	exchanged easily. Default boot mode is "boot from flash", i.e. system
-	works stand-alone.
-
-	This behaviour depends on some environment variables :
-
-	"netboot" : yes ->try dhcp/bootp and boot from network.
-	A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
-	DHCP server configuration, e.g. to provide different images to
-	different devices.
-
-	During netboot the system tries to get 3 image files:
-	1. Kernel - name + data is given during BOOTP.
-	2. Initrd - name is stored in "initrd_name"
-	3. device tree blob - name is stored in "dtb_name"
-	Fallback files are the flash versions.
diff --git a/board/matrix_vision/mvbc_p/fpga.c b/board/matrix_vision/mvbc_p/fpga.c
deleted file mode 100644
index b88f43f..0000000
--- a/board/matrix_vision/mvbc_p/fpga.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <ACEX1K.h>
-#include <command.h>
-#include "fpga.h"
-#include "mvbc_p.h"
-
-#ifdef FPGA_DEBUG
-#define fpga_debug(fmt, args...)	printf("%s: "fmt, __func__, ##args)
-#else
-#define fpga_debug(fmt, args...)
-#endif
-
-Altera_CYC2_Passive_Serial_fns altera_fns = {
-	fpga_null_fn,
-	fpga_config_fn,
-	fpga_status_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	fpga_null_fn,
-	fpga_null_fn,
-};
-
-Altera_desc cyclone2 = {
-	Altera_CYC2,
-	passive_serial,
-	Altera_EP2C8_SIZE,
-	(void *) &altera_fns,
-	NULL,
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mvbc_p_init_fpga(void)
-{
-	fpga_debug("Initialize FPGA interface\n");
-	fpga_init();
-	fpga_add(fpga_altera, &cyclone2);
-	fpga_config_fn(0, 1, 0);
-	udelay(60);
-
-	return 1;
-}
-
-int fpga_null_fn(int cookie)
-{
-	return 0;
-}
-
-int fpga_config_fn(int assert, int flush, int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-	u32 dvo = gpio->simple_dvo;
-
-	fpga_debug("SET config : %s\n", assert ? "low" : "high");
-	if (assert)
-		dvo |= FPGA_CONFIG;
-	else
-		dvo &= ~FPGA_CONFIG;
-
-	if (flush)
-		gpio->simple_dvo = dvo;
-
-	return assert;
-}
-
-int fpga_done_fn(int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-	int result = 0;
-
-	udelay(10);
-	fpga_debug("CONF_DONE check ... ");
-	if (gpio->simple_ival & FPGA_CONF_DONE) {
-		fpga_debug("high\n");
-		result = 1;
-	} else
-		fpga_debug("low\n");
-
-	return result;
-}
-
-int fpga_status_fn(int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-	int result = 0;
-
-	fpga_debug("STATUS check ... ");
-	if (gpio->sint_ival & FPGA_STATUS) {
-		fpga_debug("high\n");
-		result = 1;
-	} else
-		fpga_debug("low\n");
-
-	return result;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-	u32 dvo = gpio->simple_dvo;
-
-	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
-	if (assert_clk)
-		dvo |= FPGA_CCLK;
-	else
-		dvo &= ~FPGA_CCLK;
-
-	if (flush)
-		gpio->simple_dvo = dvo;
-
-	return assert_clk;
-}
-
-static inline int _write_fpga(u8 val)
-{
-	int i;
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-	u32 dvo = gpio->simple_dvo;
-
-	for (i=0; i<8; i++) {
-		dvo &= ~FPGA_CCLK;
-		gpio->simple_dvo = dvo;
-		dvo &= ~FPGA_DIN;
-		if (val & 1)
-			dvo |= FPGA_DIN;
-		gpio->simple_dvo = dvo;
-		dvo |= FPGA_CCLK;
-		gpio->simple_dvo = dvo;
-		val >>= 1;
-	}
-
-	return 0;
-}
-
-int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie)
-{
-	unsigned char *data = (unsigned char *) buf;
-	int i;
-
-	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
-	for (i = 0; i < len; i++)
-		_write_fpga(data[i]);
-	fpga_debug("\n");
-
-	return FPGA_SUCCESS;
-}
diff --git a/board/matrix_vision/mvbc_p/fpga.h b/board/matrix_vision/mvbc_p/fpga.h
deleted file mode 100644
index 96d3465..0000000
--- a/board/matrix_vision/mvbc_p/fpga.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-extern int mvbc_p_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_status_fn(int cookie);
-extern int fpga_config_fn(int assert, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(const void *buf, size_t len, int flush, int cookie);
-extern int fpga_null_fn(int cookie);
diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c
deleted file mode 100644
index 8faebee..0000000
--- a/board/matrix_vision/mvbc_p/mvbc_p.c
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2005-2007
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <malloc.h>
-#include <pci.h>
-#include <i2c.h>
-#include <fpga.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include "fpga.h"
-#include "mvbc_p.h"
-#include "../common/mv_common.h"
-
-#define SDRAM_MODE	0x00CD0000
-#define SDRAM_CONTROL	0x504F0000
-#define SDRAM_CONFIG1	0xD2322800
-#define SDRAM_CONFIG2	0x8AD70000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void sdram_start (int hi_addr)
-{
-	long hi_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 | hi_bit);
-
-	/* precharge all banks */
-	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
-
-	/* precharge all banks */
-	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 | hi_bit);
-
-	/* auto refresh */
-	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 | hi_bit);
-
-	/* set mode register */
-	out_be32((u32*)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32((u32*)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
-}
-
-phys_addr_t initdram (int board_type)
-{
-	ulong dramsize = 0;
-	ulong test1,
-	      test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
-
-	/* setup config registers */
-	out_be32((u32*)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((u32*)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	if (dramsize > 0)
-		out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1);
-	else
-		out_be32((u32*)MPC5XXX_SDRAM_CS0CFG, 0);
-
-	return dramsize;
-}
-
-void mvbc_init_gpio(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	printf("Ports : 0x%08x\n", gpio->port_config);
-	printf("PORCFG: 0x%08lx\n", *(vu_long*)MPC5XXX_CDM_PORCFG);
-
-	out_be32(&gpio->simple_ddr, SIMPLE_DDR);
-	out_be32(&gpio->simple_dvo, SIMPLE_DVO);
-	out_be32(&gpio->simple_ode, SIMPLE_ODE);
-	out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
-
-	out_8(&gpio->sint_ode, SINT_ODE);
-	out_8(&gpio->sint_ddr, SINT_DDR);
-	out_8(&gpio->sint_dvo, SINT_DVO);
-	out_8(&gpio->sint_inten, SINT_INTEN);
-	out_be16(&gpio->sint_itype, SINT_ITYPE);
-	out_8(&gpio->sint_gpioe, SINT_GPIOEN);
-
-	out_8((u8*)MPC5XXX_WU_GPIO_ODE, WKUP_ODE);
-	out_8((u8*)MPC5XXX_WU_GPIO_DIR, WKUP_DIR);
-	out_8((u8*)MPC5XXX_WU_GPIO_DATA_O, WKUP_DO);
-	out_8((u8*)MPC5XXX_WU_GPIO_ENABLE, WKUP_EN);
-
-	printf("simple_gpioe: 0x%08x\n", gpio->simple_gpioe);
-	printf("sint_gpioe  : 0x%08x\n", gpio->sint_gpioe);
-}
-
-int misc_init_r(void)
-{
-	char *s = getenv("reset_env");
-
-	if (!s) {
-		if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
-			return 0;
-		udelay(50000);
-		if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
-			return 0;
-		udelay(50000);
-		if (in_8((u8*)MPC5XXX_WU_GPIO_DATA_I) & MPC5XXX_GPIO_WKUP_6)
-			return 0;
-	}
-	printf(" === FACTORY RESET ===\n");
-	mv_reset_environment();
-	saveenv();
-
-	return -1;
-}
-
-int checkboard(void)
-{
-	mvbc_init_gpio();
-	printf("Board: Matrix Vision mvBlueCOUGAR-P\n");
-
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	clrbits_be32((u32*)MPC5XXX_BOOTCS_CFG, 0x1);
-}
-
-void flash_afterinit(ulong size)
-{
-	out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
-		size));
-	out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
-		size));
-	out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
-		size));
-	out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
-		size));
-}
-
-void pci_mvbc_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	unsigned char line = 0xff;
-	char *s = getenv("pci_latency");
-	u32 base;
-	u8 val = 0;
-
-	if (s)
-		val = simple_strtoul(s, NULL, 16);
-
-	if (PCI_BUS(dev) == 0) {
-		switch (PCI_DEV (dev)) {
-		case 0xa: /* FPGA */
-			line = 3;
-			pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &base);
-			printf("found FPGA - enable arbitration\n");
-			writel(0x03, (u32*)(base + 0x80c0));
-			writel(0xf0, (u32*)(base + 0x8080));
-			if (val)
-				pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
-			break;
-		case 0xb: /* LAN */
-			line = 2;
-			if (val)
-				pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, val);
-			break;
-		case 0x1a:
-			break;
-		default:
-			printf ("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV (dev));
-			break;
-		}
-		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line);
-	}
-}
-
-struct pci_controller hose = {
-	fixup_irq:pci_mvbc_fixup_irq
-};
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
-	mvbc_p_init_fpga();
-	mv_load_fpga();
-	pci_mpc5xxx_init(&hose);
-}
-
-void show_boot_progress(int val)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO;
-
-	switch(val) {
-	case BOOTSTAGE_ID_START: /* FPGA ok */
-		setbits_be32(&gpio->simple_dvo, LED_G0);
-		break;
-	case BOOTSTAGE_ID_NET_ETH_INIT:
-		setbits_be32(&gpio->simple_dvo, LED_G1);
-		break;
-	case BOOTSTAGE_ID_COPY_RAMDISK:
-		setbits_be32(&gpio->simple_dvo, LED_Y);
-		break;
-	case BOOTSTAGE_ID_RUN_OS:
-		setbits_be32(&gpio->simple_dvo, LED_R);
-		break;
-	default:
-		break;
-	}
-
-}
-
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis); /* Built in FEC comes first */
-	return pci_eth_init(bis);
-}
diff --git a/board/matrix_vision/mvbc_p/mvbc_p.h b/board/matrix_vision/mvbc_p/mvbc_p.h
deleted file mode 100644
index be1542b..0000000
--- a/board/matrix_vision/mvbc_p/mvbc_p.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#ifndef __MVBC_H__
-#define __MVBC_H__
-
-#define LED_G0          MPC5XXX_GPIO_SIMPLE_PSC2_0
-#define LED_G1          MPC5XXX_GPIO_SIMPLE_PSC2_1
-#define LED_Y           MPC5XXX_GPIO_SIMPLE_PSC2_2
-#define LED_R           MPC5XXX_GPIO_SIMPLE_PSC2_3
-#define ARB_X_EN        MPC5XXX_GPIO_WKUP_PSC2_4
-
-#define FPGA_DIN        MPC5XXX_GPIO_SIMPLE_PSC3_0
-#define FPGA_CCLK       MPC5XXX_GPIO_SIMPLE_PSC3_1
-#define FPGA_CONF_DONE  MPC5XXX_GPIO_SIMPLE_PSC3_2
-#define FPGA_CONFIG     MPC5XXX_GPIO_SIMPLE_PSC3_3
-#define FPGA_STATUS     MPC5XXX_GPIO_SINT_PSC3_4
-
-#define MAN_RST         MPC5XXX_GPIO_WKUP_PSC6_0
-#define WD_TS           MPC5XXX_GPIO_WKUP_PSC6_1
-#define WD_WDI          MPC5XXX_GPIO_SIMPLE_PSC6_2
-#define COP_PRESENT     MPC5XXX_GPIO_SIMPLE_PSC6_3
-#define FACT_RST        MPC5XXX_GPIO_WKUP_6
-#define FLASH_RBY       MPC5XXX_GPIO_WKUP_7
-
-#define SIMPLE_DDR      (LED_G0 | LED_G1 | LED_Y | LED_R | \
-			 FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI)
-#define SIMPLE_DVO      (FPGA_CONFIG)
-#define SIMPLE_ODE      (FPGA_CONFIG | LED_G0 | LED_G1 | LED_Y | LED_R)
-#define SIMPLE_GPIOEN   (LED_G0 | LED_G1 | LED_Y | LED_R | \
-			 FPGA_DIN | FPGA_CCLK | FPGA_CONF_DONE | FPGA_CONFIG |\
-			 WD_WDI | COP_PRESENT)
-
-#define SINT_ODE        0
-#define SINT_DDR        0
-#define SINT_DVO        0
-#define SINT_INTEN      0
-#define SINT_ITYPE      0
-#define SINT_GPIOEN     (FPGA_STATUS)
-
-#define WKUP_ODE        (MAN_RST)
-#define WKUP_DIR        (ARB_X_EN|MAN_RST|WD_TS)
-#define WKUP_DO         (ARB_X_EN|MAN_RST|WD_TS)
-#define WKUP_EN         (ARB_X_EN|MAN_RST|WD_TS|FACT_RST|FLASH_RBY)
-
-#endif
diff --git a/board/matrix_vision/mvbc_p/mvbc_p_autoscript b/board/matrix_vision/mvbc_p/mvbc_p_autoscript
deleted file mode 100644
index 9b21f30..0000000
--- a/board/matrix_vision/mvbc_p/mvbc_p_autoscript
+++ /dev/null
@@ -1,48 +0,0 @@
-echo
-echo "==== running autoscript ===="
-echo
-setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram}
-setenv ramkernel setenv kernel_boot \${loadaddr}
-setenv flashkernel setenv kernel_boot \${mv_kernel_addr}
-setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length}
-setenv bootfromflash run flashkernel cpird ramparam addcons e1000para addprofile bootdtb
-setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name}
-setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000
-setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup
-setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel
-if test ${console} = yes;
-then
-setenv addcons setenv bootargs \${bootargs} console=ttyPSC\${console_nr},\${baudrate}N8
-else
-setenv addcons setenv bootargs \${bootargs} console=tty0
-fi
-setenv e1000para setenv bootargs \${bootargs} e1000.TxDescriptors=256 e1000.SmartPowerDownEnable=1
-setenv set_static_ip setenv ipaddr \${static_ipaddr}
-setenv set_static_nm setenv netmask \${static_netmask}
-setenv set_static_gw setenv gatewayip \${static_gateway}
-setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask}
-setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs
-if test ${oprofile} = yes;
-then
-setenv addprofile setenv bootargs \${bootargs} profile=\${profile}
-fi
-if test ${autoscript_boot} != no;
-then
-  if test ${netboot} = yes;
-  then
-    bootp
-    if test $? = 0;
-    then
-      echo "=== bootp succeeded -> netboot ==="
-      run set_ip
-      run getdtb rundtb bootfromnet ramparam addcons e1000para addprofile bootdtb
-    else
-      echo "=== netboot failed ==="
-    fi
-  fi
-  run set_static_ip set_static_nm set_static_gw set_ip
-  echo "=== bootfromflash ==="
-  run cpdtb rundtb bootfromflash
-else
-  echo "=== boot stopped with autoscript_boot no ==="
-fi
diff --git a/board/matrix_vision/mvsmr/.gitignore b/board/matrix_vision/mvsmr/.gitignore
deleted file mode 100644
index 469f1bc..0000000
--- a/board/matrix_vision/mvsmr/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-bootscript.img
diff --git a/board/matrix_vision/mvsmr/Kconfig b/board/matrix_vision/mvsmr/Kconfig
deleted file mode 100644
index d725c5a..0000000
--- a/board/matrix_vision/mvsmr/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MVSMR
-
-config SYS_BOARD
-	default "mvsmr"
-
-config SYS_VENDOR
-	default "matrix_vision"
-
-config SYS_CONFIG_NAME
-	default "MVSMR"
-
-endif
diff --git a/board/matrix_vision/mvsmr/MAINTAINERS b/board/matrix_vision/mvsmr/MAINTAINERS
deleted file mode 100644
index ae3cf9c..0000000
--- a/board/matrix_vision/mvsmr/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MVSMR BOARD
-#M:	Andre Schwarz <andre.schwarz@matrix-vision.de>
-S:	Orphan (since 2014-03)
-F:	board/matrix_vision/mvsmr/
-F:	include/configs/MVSMR.h
-F:	configs/MVSMR_defconfig
diff --git a/board/matrix_vision/mvsmr/Makefile b/board/matrix_vision/mvsmr/Makefile
deleted file mode 100644
index cef1b76..0000000
--- a/board/matrix_vision/mvsmr/Makefile
+++ /dev/null
@@ -1,18 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2004-2008
-# Matrix-Vision GmbH, info@matrix-vision.de
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= mvsmr.o fpga.o
-
-extra-y := bootscript.img
-
-MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script
-
-$(obj)/bootscript.img: $(src)/bootscript
-	$(call cmd,mkimage)
diff --git a/board/matrix_vision/mvsmr/README.mvsmr b/board/matrix_vision/mvsmr/README.mvsmr
deleted file mode 100644
index 8e34cb7..0000000
--- a/board/matrix_vision/mvsmr/README.mvsmr
+++ /dev/null
@@ -1,55 +0,0 @@
-Matrix Vision mvSMR
--------------------
-
-1.	Board Description
-
-	The mvSMR is a 75x130mm single image processing board used
-	in automation. Power Supply is 24VDC.
-
-2	System Components
-
-2.1	CPU
-	Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
-	64MB DDR-I @ 133MHz.
-	8 MByte Nor Flash on local bus.
-	2 serial ports. Console running on ttyS0 @ 115200 8N1.
-
-2.2	PCI
-	PCI clock fixed at 33MHz due to old'n'slow Xilinx PCI core.
-
-2.3	FPGA
-	Xilinx Spartan-3 XC3S200 with PCI DMA engine.
-	Connects to Matrix Vision specific CCD/CMOS sensor interface.
-
-2.4	I2C
-	EEPROM @ 0xA0 for vendor specifics.
-	image sensor interface (slave addresses depend on sensor)
-
-3	Flash layout.
-
-	reset vector is 0x00000100, i.e. "LOWBOOT".
-
-	FF800000	u-boot
-	FF806000	u-boot script image
-	FF808000	u-boot environment
-	FF840000	FPGA raw bit file
-	FF880000	root FS
-	FFF00000	kernel
-
-4	Booting
-
-	On startup the bootscript @ FF806000 is executed. This script can be
-	exchanged easily. Default boot mode is "boot from flash", i.e. system
-	works stand-alone.
-
-	This behaviour depends on some environment variables :
-
-	"netboot" : yes ->try dhcp/bootp and boot from network.
-	A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
-	DHCP server configuration, e.g. to provide different images to
-	different devices.
-
-	During netboot the system tries to get 3 image files:
-	1. Kernel - name + data is given during BOOTP.
-	2. Initrd - name is stored in "initrd_name"
-	Fallback files are the flash versions.
diff --git a/board/matrix_vision/mvsmr/bootscript b/board/matrix_vision/mvsmr/bootscript
deleted file mode 100644
index 02c802c..0000000
--- a/board/matrix_vision/mvsmr/bootscript
+++ /dev/null
@@ -1,42 +0,0 @@
-echo
-echo "==== running autoscript ===="
-echo
-setenv boot24 'bootm ${kernel_boot} ${mv_initrd_addr_ram}'
-setenv ramkernel 'setenv kernel_boot ${loadaddr}'
-setenv flashkernel 'setenv kernel_boot ${mv_kernel_addr}'
-setenv cpird 'cp ${mv_initrd_addr} ${mv_initrd_addr_ram} ${mv_initrd_length}'
-setenv bootfromflash run flashkernel cpird addcons boot24
-setenv bootfromnet 'tftp ${mv_initrd_addr_ram} ${initrd_name};run ramkernel'
-if test ${console} = yes;
-then
-setenv addcons 'setenv bootargs ${bootargs} console=ttyS${console_nr},${baudrate}N8'
-else
-setenv addcons 'setenv bootargs ${bootargs} console=tty0'
-fi
-setenv set_static_ip 'setenv ipaddr ${static_ipaddr}'
-setenv set_static_nm 'setenv netmask ${static_netmask}'
-setenv set_static_gw 'setenv gatewayip ${static_gateway}'
-setenv set_ip 'setenv ip ${ipaddr}::${gatewayip}:${netmask}'
-if test ${servicemode} != yes;
-then
-  echo "=== forced flash mode ==="
-  run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
-fi
-if test ${autoscript_boot} != no;
-then
-  if test ${netboot} = yes;
-  then
-    bootp
-    if test $? = 0;
-    then
-      echo "=== bootp succeeded -> netboot ==="
-      run set_ip bootfromnet addcons boot24
-    else
-      echo "=== netboot failed ==="
-    fi
-  fi
-  echo "=== bootfromflash ==="
-  run set_static_ip set_static_nm set_static_gw set_ip bootfromflash
-else
-  echo "=== boot stopped with autoscript_boot no ==="
-fi
diff --git a/board/matrix_vision/mvsmr/fpga.c b/board/matrix_vision/mvsmr/fpga.c
deleted file mode 100644
index 5189925..0000000
--- a/board/matrix_vision/mvsmr/fpga.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2002
- * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
- * Keith Outwater, keith_outwater@mvis.com.
- *
- * (C) Copyright 2010
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <spartan3.h>
-#include <command.h>
-#include <asm/io.h>
-#include "fpga.h"
-#include "mvsmr.h"
-
-xilinx_spartan3_slave_serial_fns fpga_fns = {
-	fpga_pre_config_fn,
-	fpga_pgm_fn,
-	fpga_clk_fn,
-	fpga_init_fn,
-	fpga_done_fn,
-	fpga_wr_fn,
-	0
-};
-
-xilinx_desc spartan3 = {
-	xilinx_spartan2,
-	slave_serial,
-	XILINX_XC3S200_SIZE,
-	(void *) &fpga_fns,
-	0,
-};
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int mvsmr_init_fpga(void)
-{
-	fpga_init();
-	fpga_add(fpga_xilinx, &spartan3);
-
-	return 1;
-}
-
-int fpga_init_fn(int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (in_be32(&gpio->simple_ival) & FPGA_CONFIG)
-		return 0;
-
-	return 1;
-}
-
-int fpga_done_fn(int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	int result = 0;
-
-	udelay(10);
-	if (in_be32(&gpio->simple_ival) & FPGA_DONE)
-		result = 1;
-
-	return result;
-}
-
-int fpga_pgm_fn(int assert, int flush, int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (!assert)
-		setbits_8(&gpio->sint_dvo, FPGA_STATUS);
-	else
-		clrbits_8(&gpio->sint_dvo, FPGA_STATUS);
-
-	return assert;
-}
-
-int fpga_clk_fn(int assert_clk, int flush, int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (assert_clk)
-		setbits_be32(&gpio->simple_dvo, FPGA_CCLK);
-	else
-		clrbits_be32(&gpio->simple_dvo, FPGA_CCLK);
-
-	return assert_clk;
-}
-
-int fpga_wr_fn(int assert_write, int flush, int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	if (assert_write)
-		setbits_be32(&gpio->simple_dvo, FPGA_DIN);
-	else
-		clrbits_be32(&gpio->simple_dvo, FPGA_DIN);
-
-	return assert_write;
-}
-
-int fpga_pre_config_fn(int cookie)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-
-	setbits_8(&gpio->sint_dvo, FPGA_STATUS);
-
-	return 0;
-}
diff --git a/board/matrix_vision/mvsmr/fpga.h b/board/matrix_vision/mvsmr/fpga.h
deleted file mode 100644
index 7ef878b..0000000
--- a/board/matrix_vision/mvsmr/fpga.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * (C) Copyright 2008
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-extern int mvsmr_init_fpga(void);
-
-extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
-extern int fpga_init_fn(int cookie);
-extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
-extern int fpga_wr_fn(int assert_write, int flush, int cookie);
-extern int fpga_done_fn(int cookie);
-extern int fpga_pre_config_fn(int cookie);
diff --git a/board/matrix_vision/mvsmr/mvsmr.c b/board/matrix_vision/mvsmr/mvsmr.c
deleted file mode 100644
index 2c51389..0000000
--- a/board/matrix_vision/mvsmr/mvsmr.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2005-2010
- * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <malloc.h>
-#include <pci.h>
-#include <i2c.h>
-#include <fpga.h>
-#include <environment.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include "fpga.h"
-#include "mvsmr.h"
-#include "../common/mv_common.h"
-
-#define SDRAM_DDR	1
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x715f0f00
-#define SDRAM_CONFIG1	0xd3722930
-#define SDRAM_CONFIG2	0x46770000
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static void sdram_start(int hi_addr)
-{
-	long hi_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000000 |
-		hi_bit);
-
-	/* precharge all banks */
-	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
-		hi_bit);
-
-	/* set mode register: extended mode */
-	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
-
-	/* set mode register: reset DLL */
-	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
-
-	/* precharge all banks */
-	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000002 |
-		hi_bit);
-
-	/* auto refresh */
-	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | 0x80000004 |
-		hi_bit);
-
-	/* set mode register */
-	out_be32((u32 *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
-
-	/* normal operation */
-	out_be32((u32 *)MPC5XXX_SDRAM_CTRL, SDRAM_CONTROL | hi_bit);
-}
-
-phys_addr_t initdram(int board_type)
-{
-	ulong dramsize = 0;
-	ulong test1,
-	      test2;
-
-	/* setup SDRAM chip selects */
-	out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e);
-
-	/* setup config registers */
-	out_be32((u32 *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
-	out_be32((u32 *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	if (dramsize > 0)
-		out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0x13 +
-			__builtin_ffs(dramsize >> 20) - 1);
-	else
-		out_be32((u32 *)MPC5XXX_SDRAM_CS0CFG, 0);
-
-	return dramsize;
-}
-
-void mvsmr_init_gpio(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_wu_gpio *wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-	struct mpc5xxx_gpt_0_7 *timers = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
-
-	printf("Ports : 0x%08x\n", gpio->port_config);
-	printf("PORCFG: 0x%08x\n", in_be32((unsigned *)MPC5XXX_CDM_PORCFG));
-
-	out_be32(&gpio->simple_ddr, SIMPLE_DDR);
-	out_be32(&gpio->simple_dvo, SIMPLE_DVO);
-	out_be32(&gpio->simple_ode, SIMPLE_ODE);
-	out_be32(&gpio->simple_gpioe, SIMPLE_GPIOEN);
-
-	out_8(&gpio->sint_ode, SINT_ODE);
-	out_8(&gpio->sint_ddr, SINT_DDR);
-	out_8(&gpio->sint_dvo, SINT_DVO);
-	out_8(&gpio->sint_inten, SINT_INTEN);
-	out_be16(&gpio->sint_itype, SINT_ITYPE);
-	out_8(&gpio->sint_gpioe, SINT_GPIOEN);
-
-	out_8(&wu_gpio->ode, WKUP_ODE);
-	out_8(&wu_gpio->ddr, WKUP_DIR);
-	out_8(&wu_gpio->dvo, WKUP_DO);
-	out_8(&wu_gpio->enable, WKUP_EN);
-
-	out_be32(&timers->gpt0.emsr, 0x00000234); /* OD output high */
-	out_be32(&timers->gpt1.emsr, 0x00000234);
-	out_be32(&timers->gpt2.emsr, 0x00000234);
-	out_be32(&timers->gpt3.emsr, 0x00000234);
-	out_be32(&timers->gpt4.emsr, 0x00000234);
-	out_be32(&timers->gpt5.emsr, 0x00000234);
-	out_be32(&timers->gpt6.emsr, 0x00000024); /* push-pull output low */
-	out_be32(&timers->gpt7.emsr, 0x00000024);
-}
-
-int misc_init_r(void)
-{
-	char *s = getenv("reset_env");
-
-	if (s) {
-		printf(" === FACTORY RESET ===\n");
-		mv_reset_environment();
-		saveenv();
-	}
-
-	return -1;
-}
-
-void mvsmr_get_dbg_present(void)
-{
-	struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
-	struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)MPC5XXX_PSC1;
-
-	if (in_be32(&gpio->simple_ival) & COP_PRESENT) {
-		setenv("dbg_present", "no\0");
-		setenv("bootstopkey", "abcdefghijklmnopqrstuvwxyz\0");
-	} else {
-		setenv("dbg_present", "yes\0");
-		setenv("bootstopkey", "s\0");
-		setbits_8(&psc->command, PSC_RX_ENABLE);
-	}
-}
-
-void mvsmr_get_service_mode(void)
-{
-	struct mpc5xxx_wu_gpio *wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-
-	if (in_8(&wu_gpio->ival) & SERVICE_MODE)
-		setenv("servicemode", "no\0");
-	else
-		setenv("servicemode", "yes\0");
-}
-
-int mvsmr_get_mac(void)
-{
-	unsigned char mac[6];
-	struct mpc5xxx_wu_gpio *wu_gpio =
-		(struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
-
-	if (in_8(&wu_gpio->ival) & LAN_PRSNT) {
-		setenv("lan_present", "no\0");
-		return -1;
-	} else
-		setenv("lan_present", "yes\0");
-
-	i2c_read(0x50, 0, 1, mac, 6);
-
-	eth_setenv_enetaddr("ethaddr", mac);
-
-	return 0;
-}
-
-int checkboard(void)
-{
-	mvsmr_init_gpio();
-	printf("Board: Matrix Vision mvSMR\n");
-
-	return 0;
-}
-
-void flash_preinit(void)
-{
-	/*
-	 * Now, when we are in RAM, enable flash write
-	 * access for detection process.
-	 * Note that CS_BOOT cannot be cleared when
-	 * executing in flash.
-	 */
-	clrbits_be32((u32 *)MPC5XXX_BOOTCS_CFG, 0x1);
-}
-
-void flash_afterinit(ulong size)
-{
-	out_be32((u32 *)MPC5XXX_BOOTCS_START,
-		START_REG(CONFIG_SYS_BOOTCS_START | size));
-	out_be32((u32 *)MPC5XXX_CS0_START,
-		START_REG(CONFIG_SYS_BOOTCS_START | size));
-	out_be32((u32 *)MPC5XXX_BOOTCS_STOP,
-		STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
-	out_be32((u32 *)MPC5XXX_CS0_STOP,
-		STOP_REG(CONFIG_SYS_BOOTCS_START | size, size));
-}
-
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
-	mvsmr_get_dbg_present();
-	mvsmr_get_service_mode();
-	mvsmr_init_fpga();
-	mv_load_fpga();
-	pci_mpc5xxx_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
-	if (!mvsmr_get_mac())
-		return cpu_eth_init(bis);
-
-	return pci_eth_init(bis);
-}
diff --git a/board/matrix_vision/mvsmr/mvsmr.h b/board/matrix_vision/mvsmr/mvsmr.h
deleted file mode 100644
index b8320f1..0000000
--- a/board/matrix_vision/mvsmr/mvsmr.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#include <pci.h>
-
-extern void pci_mpc5xxx_init(struct pci_controller *);
-
-#define FPGA_DIN	MPC5XXX_GPIO_SIMPLE_PSC3_0
-#define FPGA_CCLK	MPC5XXX_GPIO_SIMPLE_PSC3_1
-#define FPGA_DONE	MPC5XXX_GPIO_SIMPLE_PSC3_2
-#define FPGA_CONFIG	MPC5XXX_GPIO_SIMPLE_PSC3_3
-#define FPGA_STATUS	MPC5XXX_GPIO_SINT_PSC3_4
-#define S_FPGA_DIN	MPC5XXX_GPIO_SINT_PSC3_5
-#define S_FPGA_CCLK	MPC5XXX_GPIO_SIMPLE_PSC3_6
-#define S_FPGA_DONE	MPC5XXX_GPIO_SIMPLE_PSC3_7
-#define S_FPGA_CONFIG	MPC5XXX_GPIO_SINT_PSC3_8
-#define S_FPGA_STATUS	MPC5XXX_GPIO_WKUP_PSC3_9
-
-#define MAN_RST		MPC5XXX_GPIO_WKUP_PSC6_0
-#define WD_TS		MPC5XXX_GPIO_WKUP_PSC6_1
-#define WD_WDI		MPC5XXX_GPIO_SIMPLE_PSC6_2
-#define COP_PRESENT	MPC5XXX_GPIO_SIMPLE_PSC6_3
-#define SERVICE_MODE	MPC5XXX_GPIO_WKUP_6
-#define FLASH_RBY	MPC5XXX_GPIO_WKUP_7
-#define UART_EN1	MPC5XXX_GPIO_WKUP_PSC1_4
-#define LAN_PRSNT	MPC5XXX_GPIO_WKUP_PSC2_4
-
-#define SIMPLE_DDR	(FPGA_DIN | FPGA_CCLK | FPGA_CONFIG | WD_WDI |\
-			 S_FPGA_CCLK)
-#define SIMPLE_DVO	(FPGA_CONFIG)
-#define SIMPLE_ODE	(FPGA_CONFIG)
-#define SIMPLE_GPIOEN	(FPGA_DIN | FPGA_CCLK | FPGA_DONE | FPGA_CONFIG |\
-			 S_FPGA_CCLK | S_FPGA_DONE | WD_WDI | COP_PRESENT)
-
-#define SINT_ODE	0x1
-#define SINT_DDR	0x3
-#define SINT_DVO	0x1
-#define SINT_INTEN	0
-#define SINT_ITYPE	0
-#define SINT_GPIOEN	(FPGA_STATUS | S_FPGA_DIN | S_FPGA_CONFIG)
-
-#define WKUP_ODE	(MAN_RST | S_FPGA_STATUS)
-#define WKUP_DIR	(MAN_RST | WD_TS | S_FPGA_STATUS)
-#define WKUP_DO		(MAN_RST | WD_TS | S_FPGA_STATUS)
-#define WKUP_EN		(MAN_RST | WD_TS | S_FPGA_STATUS | SERVICE_MODE |\
-			 FLASH_RBY | UART_EN1 | LAN_PRSNT)
diff --git a/board/matrix_vision/mvsmr/u-boot.lds b/board/matrix_vision/mvsmr/u-boot.lds
deleted file mode 100644
index e885b7c..0000000
--- a/board/matrix_vision/mvsmr/u-boot.lds
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- * (C) Copyright 2010
- * André Schwarz, Matrix Vision GmbH, as@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
-  /* Read-only sections, merged into text segment: */
-  .text      :
-  {
-    /* WARNING - the following is hand-optimized to fit within  */
-    /* the first two sectors (=8KB) of our S29GL flash chip */
-    arch/powerpc/cpu/mpc5xxx/start.o	(.text*)
-    arch/powerpc/cpu/mpc5xxx/traps.o	(.text*)
-    board/matrix_vision/common/built-in.o	(.text*)
-
-    /* This is only needed to force failure if size of above code will ever */
-    /* increase and grow into reserved space. */
-    . = ALIGN(0x2000);	/* location counter has to be 0x4000 now */
-    . += 0x4000;	/* ->0x8000, i.e. move to env_offset */
-
-    . = env_offset;	/* ld error as soon as above ALIGN misplaces lc */
-    common/env_embedded.o        (.ppcenv)
-
-    *(.text*)
-    . = ALIGN(16);
-    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-  }
-
-  /* Read-write section, merged into data segment: */
-  . = (. + 0x0FFF) & 0xFFFFF000;
-  _erotext = .;
-  PROVIDE (erotext = .);
-  .reloc   :
-  {
-    _GOT2_TABLE_ = .;
-    KEEP(*(.got2))
-    KEEP(*(.got))
-    PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
-    _FIXUP_TABLE_ = .;
-    KEEP(*(.fixup))
-  }
-  __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
-  .data    :
-  {
-    *(.data*)
-    *(.sdata*)
-  }
-  _edata  =  .;
-  PROVIDE (edata = .);
-
-  . = .;
-
-  . = ALIGN(4);
-  .u_boot_list : {
-	KEEP(*(SORT(.u_boot_list*)));
-  }
-
-
-  . = .;
-  __start___ex_table = .;
-  __ex_table : { *(__ex_table) }
-  __stop___ex_table = .;
-
-  . = ALIGN(4096);
-  __init_begin = .;
-  .text.init : { *(.text.init) }
-  .data.init : { *(.data.init) }
-  . = ALIGN(4096);
-  __init_end = .;
-
-  __bss_start = .;
-  .bss (NOLOAD)       :
-  {
-   *(.bss*)
-   *(.sbss*)
-   . = ALIGN(4);
-  }
-  __bss_end = . ;
-  PROVIDE (end = .);
-}
diff --git a/configs/MVBC_P_defconfig b/configs/MVBC_P_defconfig
deleted file mode 100644
index b0351fd..0000000
--- a/configs/MVBC_P_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_SYS_EXTRA_OPTIONS="MVBC_P"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MVBC_P=y
diff --git a/configs/MVSMR_defconfig b/configs/MVSMR_defconfig
deleted file mode 100644
index a84c173..0000000
--- a/configs/MVSMR_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_MVSMR=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 3caa8cf..1dcdcc7 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+MVBC_P           powerpc     mpc5xxx        -           -           Andre Schwarz <andre.schwarz@matrix-vision.de>
+MVSMR            powerpc     mpc5xxx        -           -           Andre Schwarz <andre.schwarz@matrix-vision.de>
 MERGERBOX        powerpc     mpc83xx        -           -           Andre Schwarz <andre.schwarz@matrix-vision.de>
 MVBLM7           powerpc     mpc83xx        -           -           Andre Schwarz <andre.schwarz@matrix-vision.de>
 bluestone        powerpc     ppc4xx         -           -           Tirumala Marri <tmarri@apm.com>
diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h
deleted file mode 100644
index 1ab2b3d..0000000
--- a/include/configs/MVBC_P.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2008
- * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-#define CONFIG_MPC5200 	1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFF800000
-#endif
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
-
-#define CONFIG_MISC_INIT_R	1
-
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-#define CONFIG_PSC_CONSOLE	1
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-#undef	CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-#define CONFIG_HIGH_BATS	1
-
-#define MV_CI			mvBlueCOUGAR-P
-#define MV_VCI			mvBlueCOUGAR-P
-#define MV_FPGA_DATA		0xff860000
-#define MV_FPGA_SIZE		0
-#define MV_KERNEL_ADDR		0xffd00000
-#define MV_INITRD_ADDR		0xff900000
-#define MV_INITRD_LENGTH	0x00400000
-#define MV_SCRATCH_ADDR		0x00000000
-#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH
-#define MV_SCRIPT_ADDR		0xff840000
-#define MV_SCRIPT_ADDR2		0xff850000
-#define MV_DTB_ADDR		0xfffc0000
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM	0x00100000
-#define MV_DTB_ADDR_RAM		0x00600000
-#define MV_INITRD_ADDR_RAM	0x01000000
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_CPU			"PowerPC,5200@0"
-#define OF_SOC			"soc5200@f0000000"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define MV_DTB_NAME		mvbc-p.dtb
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/*
- * Supported commands
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_I2C
-
-#undef CONFIG_WATCHDOG
-
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_LIB_RAND
-
-/*
- * Autoboot
- */
-#define CONFIG_BOOTDELAY		2
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR 	"s"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_RESET_TO_RETRY		1000
-
-#define CONFIG_BOOTCOMMAND	"if imi ${script_addr}; \
-					then source ${script_addr};	\
-					else source ${script_addr2};	\
-				fi;"
-
-#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs"
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"console_nr=0\0"					\
-	"console=yes\0"						\
-	"stdin=serial\0"					\
-	"stdout=serial\0"					\
-	"stderr=serial\0"					\
-	"fpga=0\0"						\
-	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
-	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
-	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
-	"script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0"		\
-	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
-	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
-	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
-	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
-	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
-	"mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0"			\
-	"mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"		\
-	"dtb_name=" __stringify(MV_DTB_NAME) "\0"			\
-	"mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"		\
-	"mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"	\
-	"mv_version=" U_BOOT_VERSION "\0"			\
-	"dhcp_client_id=" __stringify(MV_CI) "\0"			\
-	"dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"	\
-	"netretry=no\0"						\
-	"use_static_ipaddr=no\0"				\
-	"static_ipaddr=192.168.90.10\0"				\
-	"static_netmask=255.255.255.0\0"			\
-	"static_gateway=0.0.0.0\0"				\
-	"initrd_name=uInitrd.mvbc-p-rfs\0"			\
-	"zcip=no\0"						\
-	"netboot=yes\0"						\
-	"mvtest=Ff\0"						\
-	"tried_bootfromflash=no\0"				\
-	"tried_bootfromnet=no\0"				\
-	"use_dhcp=yes\0"					\
-	"gev_start=yes\0"					\
-	"mvbcdma_debug=0\0"					\
-	"mvbcia_debug=0\0"					\
-	"propdev_debug=0\0"					\
-	"gevss_debug=0\0"					\
-	"watchdog=1\0"						\
-	"sensor_cnt=1\0"					\
-	""
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
-#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
-
-/*
- * Flash configuration
- */
-#undef 	CONFIG_FLASH_16BIT
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-#define CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#undef	CONFIG_SYS_FLASH_PROTECTION
-
-#define CONFIG_ENV_ADDR		0xFFFE0000
-#define CONFIG_ENV_SIZE		0x10000
-#define CONFIG_ENV_SECT_SIZE	0x10000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR+CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_MODULE	1
-#define CONFIG_SYS_I2C_SPEED	86000
-#define CONFIG_SYS_I2C_SLAVE	0x7F
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_E1000
-#define CONFIG_E1000_FALLBACK_MAC	{ 0xb6, 0xb4, 0x45, 0xeb, 0xfb, 0xc0 }
-#undef CONFIG_MPC5xxx_FEC
-#undef CONFIG_PHY_ADDR
-#define CONFIG_NETDEV		eth0
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#undef 	CONFIG_SYS_LONGHELP
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CBSIZE		1024
-#else
-#define CONFIG_SYS_CBSIZE		256
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x00800000
-#define CONFIG_SYS_MEMTEST_END		0x02f00000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x02000000
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 	0x00200000
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x20000004
-
-#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047800
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x000000f0
-#define CONFIG_SYS_CS_DEADCYCLE	0x33333303
-
-#define CONFIG_SYS_RESET_ADDRESS	0x00000100
-
-#undef FPGA_DEBUG
-#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA	1
-#define CONFIG_FPGA_CYCLON2	1
-#define CONFIG_FPGA_COUNT	1
-
-#endif
diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h
deleted file mode 100644
index 27f730d..0000000
--- a/include/configs/MVSMR.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * (C) Copyright 2003-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004-2010
- * Matrix-Vision GmbH, andre.schwarz@matrix-vision.de
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <version.h>
-
-#define CONFIG_MPC5200 	1
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFF800000
-#endif
-#define CONFIG_SYS_LDSCRIPT	"board/matrix_vision/mvsmr/u-boot.lds"
-
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
-
-#define CONFIG_MISC_INIT_R	1
-
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5
-#endif
-
-#define CONFIG_PSC_CONSOLE	1
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200,\
-						230400}
-
-#define CONFIG_PCI		1
-#define CONFIG_PCI_PNP		1
-#undef	CONFIG_PCI_SCAN_SHOW
-#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1
-
-#define CONFIG_PCI_MEM_BUS	0x40000000
-#define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
-#define CONFIG_PCI_MEM_SIZE	0x10000000
-
-#define CONFIG_PCI_IO_BUS	0x50000000
-#define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
-#define CONFIG_PCI_IO_SIZE	0x01000000
-
-#define CONFIG_SYS_XLB_PIPELINING	1
-#define CONFIG_HIGH_BATS	1
-
-#define MV_CI			mvSMR
-#define MV_VCI			mvSMR
-#define MV_FPGA_DATA		0xff840000
-#define MV_FPGA_SIZE		0x1ff88
-#define MV_KERNEL_ADDR		0xfff00000
-#define MV_SCRIPT_ADDR		0xff806000
-#define MV_INITRD_ADDR		0xff880000
-#define MV_INITRD_LENGTH	0x00240000
-#define MV_SCRATCH_ADDR		0xffcc0000
-#define MV_SCRATCH_LENGTH	MV_INITRD_LENGTH
-
-#define CONFIG_SHOW_BOOT_PROGRESS 1
-
-#define MV_KERNEL_ADDR_RAM	0x00100000
-#define MV_INITRD_ADDR_RAM	0x00400000
-
-/*
- * Supported commands
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SDRAM
-
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_NTPSERVER
-#define CONFIG_BOOTP_RANDOM_DELAY
-#define CONFIG_BOOTP_SEND_HOSTNAME
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_VENDOREX
-#define CONFIG_LIB_RAND
-
-/*
- * Autoboot
- */
-#define CONFIG_BOOTDELAY		1
-#define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_STOP_STR 	"abcdefg"
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
-#define CONFIG_BOOTCOMMAND      "source ${script_addr}"
-#define CONFIG_BOOTARGS		"root=/dev/ram ro rootfstype=squashfs" \
-					" allocate=6M"
-
-#define CONFIG_EXTRA_ENV_SETTINGS				\
-	"console_nr=0\0"					\
-	"console=no\0"						\
-	"stdin=serial\0"					\
-	"stdout=serial\0"					\
-	"stderr=serial\0"					\
-	"fpga=0\0"						\
-	"fpgadata=" __stringify(MV_FPGA_DATA) "\0"			\
-	"fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"		\
-	"mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0"		\
-	"mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"	\
-	"script_addr=" __stringify(MV_SCRIPT_ADDR) "\0"		\
-	"mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0"		\
-	"mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"	\
-	"mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0"	\
-	"mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0"		\
-	"mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0"	\
-	"mv_version=" U_BOOT_VERSION "\0"			\
-	"dhcp_client_id=" __stringify(MV_CI) "\0"			\
-	"dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0"	\
-	"netretry=no\0"						\
-	"use_static_ipaddr=no\0"				\
-	"static_ipaddr=192.168.0.101\0"				\
-	"static_netmask=255.255.255.0\0"			\
-	"static_gateway=0.0.0.0\0"				\
-	"initrd_name=uInitrd.mvsmr-rfs\0"			\
-	"zcip=yes\0"						\
-	"netboot=no\0"						\
-	""
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK
-
-/*
- * Flash configuration
- */
-#undef 	CONFIG_FLASH_16BIT
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	50000
-#define CONFIG_SYS_FLASH_WRITE_TOUT	1000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-#define CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_FLASH_SIZE		0x00800000
-
-/*
- * Environment settings
- */
-#define CONFIG_ENV_IS_IN_FLASH
-#undef	CONFIG_SYS_FLASH_PROTECTION
-#define	CONFIG_OVERWRITE_ETHADDR_ONCE
-
-#define CONFIG_ENV_OFFSET	0x8000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE	0x2000
-
-/* used by linker script to wrap code around */
-#define CONFIG_SCRIPT_OFFSET	0x6000
-#define CONFIG_SCRIPT_SECT_SIZE	0x2000
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR		0xF0000000
-#define CONFIG_SYS_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR	0x80000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT		1
-#endif
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN		(512 << 10)
-#define CONFIG_SYS_MALLOC_LEN		(512 << 10)
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_MODULE	1
-#define CONFIG_SYS_I2C_SPEED	86000
-#define CONFIG_SYS_I2C_SLAVE	0x7F
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_NET_RETRY_COUNT 5
-
-#define CONFIG_MPC5xxx_FEC
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR		0x00
-#define CONFIG_NETDEV		eth0
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_CMDLINE_EDITING
-#undef 	CONFIG_SYS_LONGHELP
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CBSIZE		1024
-#else
-#define CONFIG_SYS_CBSIZE		256
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS		16
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START	0x00800000
-#define CONFIG_SYS_MEMTEST_END		0x02f00000
-
-/* default load address */
-#define CONFIG_SYS_LOAD_ADDR		0x02000000
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR 		0x00200000
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x00050044
-
-#define CONFIG_SYS_HID0_INIT		(HID0_ICE | HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-#define CONFIG_SYS_BOOTCS_CFG		0x00047800
-#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_CS_BURST		0x000000f0
-#define CONFIG_SYS_CS_DEADCYCLE		0x33333303
-
-#define CONFIG_SYS_RESET_ADDRESS	0x00000100
-
-#undef FPGA_DEBUG
-#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
-#define CONFIG_FPGA
-#define CONFIG_FPGA_XILINX	1
-#define CONFIG_FPGA_SPARTAN2	1
-#define CONFIG_FPGA_COUNT	1
-
-#endif