summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorWolfgang Denk <wd@denx.de>2007-03-16 22:20:36 +0100
committerWolfgang Denk <wd@denx.de>2007-03-16 22:20:36 +0100
commit87e0662762b78ed7731f14add60ba0edb0479252 (patch)
tree3e287b224b2bb1e2dce1b129b5d970c4c2aa5443
parenta7090b993d3d4d2221ac3f33e6cb1d1b2ccc6bf0 (diff)
parent8423e5e31a7235d05a482627315fb11d49c17bd7 (diff)
downloadu-boot-imx-87e0662762b78ed7731f14add60ba0edb0479252.zip
u-boot-imx-87e0662762b78ed7731f14add60ba0edb0479252.tar.gz
u-boot-imx-87e0662762b78ed7731f14add60ba0edb0479252.tar.bz2
Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xx
-rw-r--r--board/amcc/ebony/init.S77
-rw-r--r--include/configs/PCI405.h11
-rw-r--r--include/configs/ebony.h5
3 files changed, 28 insertions, 65 deletions
diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S
index cc8f8b4..c86076e 100644
--- a/board/amcc/ebony/init.S
+++ b/board/amcc/ebony/init.S
@@ -22,53 +22,7 @@
#include <ppc_asm.tmpl>
#include <config.h>
-
-/* General */
-#define TLB_VALID 0x00000200
-
-/* Supported page sizes */
-
-#define SZ_1K 0x00000000
-#define SZ_4K 0x00000010
-#define SZ_16K 0x00000020
-#define SZ_64K 0x00000030
-#define SZ_256K 0x00000040
-#define SZ_1M 0x00000050
-#define SZ_16M 0x00000070
-#define SZ_256M 0x00000090
-
-/* Storage attributes */
-#define SA_W 0x00000800 /* Write-through */
-#define SA_I 0x00000400 /* Caching inhibited */
-#define SA_M 0x00000200 /* Memory coherence */
-#define SA_G 0x00000100 /* Guarded */
-#define SA_E 0x00000080 /* Endian */
-
-/* Access control */
-#define AC_X 0x00000024 /* Execute */
-#define AC_W 0x00000012 /* Write */
-#define AC_R 0x00000009 /* Read */
-
-/* Some handy macros */
-
-#define EPN(e) ((e) & 0xfffffc00)
-#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a) ( (a)&0x00000fbf )
-
-#define tlbtab_start\
- mflr r1 ;\
- bl 0f ;
-
-#define tlbtab_end\
- .long 0, 0, 0 ; \
-0: mflr r0 ; \
- mtlr r1 ; \
- blr ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
- .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
+#include <asm-ppc/mmu.h>
/**************************************************************************
* TLB TABLE
@@ -81,16 +35,23 @@
*
*************************************************************************/
- .section .bootpg,"ax"
- .globl tlbtab
+ .section .bootpg,"ax"
+ .globl tlbtab
tlbtab:
- tlbtab_start
- tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
- tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
- tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
- tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
- tlbtab_end
+ tlbtab_start
+
+ tlbentry(0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR(2) detection
+ * routine.
+ */
+
+ tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
+ tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
+ tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
+ tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+ tlbtab_end
diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h
index 9d5c4f4..027dd22 100644
--- a/include/configs/PCI405.h
+++ b/include/configs/PCI405.h
@@ -1,6 +1,9 @@
/*
+ * (C) Copyright 2007
+ * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
+ *
* (C) Copyright 2001-2004
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -32,8 +35,6 @@
* High Level Configuration Options
* (easy to change)
*/
-#define CONFIG_IDENT_STRING " $Name: esd_PCI405_05_07_28 $"
-
#define CONFIG_405GP 1 /* This is a PPC405 CPU */
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_PCI405 1 /* ...on a PCI405 board */
@@ -53,9 +54,9 @@
"mem_linux=14336k\0" \
"optargs=panic=0\0" \
"ramargs=setenv bootargs mem=$mem_linux root=/dev/ram rw\0" \
- "addcon=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
+ "addcons=setenv bootargs $bootargs console=ttyS0,$baudrate $optargs\0" \
""
-#define CONFIG_BOOTCOMMAND "run ramargs;run addcon;loadpci"
+#define CONFIG_BOOTCOMMAND "run ramargs;run addcons;loadpci"
#define CONFIG_PREBOOT /* enable preboot variable */
diff --git a/include/configs/ebony.h b/include/configs/ebony.h
index 6c4d7cc..a42319b 100644
--- a/include/configs/ebony.h
+++ b/include/configs/ebony.h
@@ -133,8 +133,9 @@
/*-----------------------------------------------------------------------
* DDR SDRAM
*----------------------------------------------------------------------*/
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
-#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
+#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
+#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
+#define CONFIG_PROG_SDRAM_TLB 1 /* setup SDRAM TLB's dynamically*/
/*-----------------------------------------------------------------------
* I2C