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authorYork Sun <yorksun@freescale.com>2014-06-23 15:36:44 -0700
committerYork Sun <yorksun@freescale.com>2014-07-22 16:25:54 -0700
commit8340e7ac86ad3c59956e8f0bd627b741e5209439 (patch)
tree0460d0395f63b1cee89ae8dfe5479ace02bb5c50
parent6666017f44e39ec0385e3c7736b8c9af46cf4f08 (diff)
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driver/ddr: Fix DDR4 driver for ARM
Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
-rw-r--r--arch/arm/include/asm/arch-fsl-lsch3/config.h4
-rw-r--r--arch/arm/include/asm/io.h1
-rw-r--r--arch/powerpc/include/asm/io.h3
-rw-r--r--drivers/ddr/fsl/fsl_ddr_gen4.c7
4 files changed, 13 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index c1c718e..b17410a 100644
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -43,7 +43,11 @@
/* DDR */
#define CONFIG_SYS_FSL_DDR_LE
#define CONFIG_VERY_BIG_RAM
+#ifdef CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_FSL_DDRC_GEN4
+#else
#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
+#endif
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 214f3ea..6d18eb3 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -136,6 +136,7 @@ extern inline void __raw_readsl(unsigned long addr, void *data, int longlen)
* TODO: The kernel offers some more advanced versions of barriers, it might
* have some advantages to use them instead of the simple one here.
*/
+#define mb() asm volatile("dsb sy" : : : "memory")
#define dmb() __asm__ __volatile__ ("" : : : "memory")
#define __iormb() dmb()
#define __iowmb() dmb()
diff --git a/arch/powerpc/include/asm/io.h b/arch/powerpc/include/asm/io.h
index d8b7b97..a5257e9 100644
--- a/arch/powerpc/include/asm/io.h
+++ b/arch/powerpc/include/asm/io.h
@@ -123,6 +123,9 @@ static inline void isync(void)
#define iobarrier_r() eieio()
#define iobarrier_w() eieio()
+#define mb() sync()
+#define isb() isync()
+
/*
* Non ordered and non-swapping "raw" accessors
*/
diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index 7cd878a..bfc76b3 100644
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -8,6 +8,7 @@
#include <asm/io.h>
#include <fsl_ddr_sdram.h>
#include <asm/processor.h>
+#include <fsl_immap.h>
#include <fsl_ddr.h>
#if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
@@ -183,12 +184,14 @@ step2:
* we choose the max, that is 500 us for all of case.
*/
udelay(500);
- asm volatile("sync;isync");
+ mb();
+ isb();
/* Let the controller go */
temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
- asm volatile("sync;isync");
+ mb();
+ isb();
total_gb_size_per_controller = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {