summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPeng Fan <Peng.Fan@freescale.com>2015-06-11 18:19:45 +0800
committerPeng Fan <Peng.Fan@freescale.com>2015-06-12 14:47:11 +0800
commit5cab58016a032ea364c8e5df3994ac51fdf60b0a (patch)
tree645e888ee0317c0b6f0080b460f63194efb11754
parent0d4904f5929cecd66f0b60cf8ebdcb0e6a2f733e (diff)
downloadu-boot-imx-5cab58016a032ea364c8e5df3994ac51fdf60b0a.zip
u-boot-imx-5cab58016a032ea364c8e5df3994ac51fdf60b0a.tar.gz
u-boot-imx-5cab58016a032ea364c8e5df3994ac51fdf60b0a.tar.bz2
MLK-11028 imx: mx6qp change L2 prefetch offset to 0
Change L2 prefetch offset to 0 to make system stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
-rw-r--r--arch/arm/cpu/armv7/mx6/soc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index febf96e..0375996 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -985,7 +985,7 @@ void v7_outer_cache_enable(void)
/* Turn on the L2 I/D prefetch, double linefill */
/* Set prefetch offset with any value except 23 as per errata 765569 */
- val |= 0x7000000f;
+ val |= 0x70000000;
/*
* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0