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authorAlison Wang <b18965@freescale.com>2014-09-05 13:52:38 +0800
committerYork Sun <yorksun@freescale.com>2014-09-08 10:30:33 -0700
commit52d00a812a29974e660f64a8839ddb550dca5290 (patch)
tree396d90c9244e58992aa55f3b86450b11958b677a
parentd2614ea0ffda9d7c0d049f0fa5b23ce390bcb7a8 (diff)
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ls102xa: etsec: Add etsec support for LS102xA
This patch is to add etsec support for LS102xA. First, Little-endian descriptor mode should be enabled. So RxBDs and TxBDs are interpreted with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET are different from PowerPC, redefine them for LS1021xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
-rw-r--r--drivers/net/tsec.c7
-rw-r--r--include/tsec.h7
2 files changed, 13 insertions, 1 deletions
diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index e9138f0..79d6561 100644
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -20,6 +20,7 @@
#include <fsl_mdio.h>
#include <asm/errno.h>
#include <asm/processor.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -270,6 +271,9 @@ void redundant_init(struct eth_device *dev)
out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102XA
+ setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
do {
uint16_t status;
@@ -366,6 +370,9 @@ static void startup_tsec(struct eth_device *dev)
out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
+#ifdef CONFIG_LS102XA
+ setbits_be32(&regs->dmactrl, DMACTRL_LE);
+#endif
}
/* This returns the status bits of the device. The return value
diff --git a/include/tsec.h b/include/tsec.h
index 2054715..1119d2c 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -20,10 +20,14 @@
#include <net.h>
#include <config.h>
#include <phy.h>
-#include <fsl_mdio.h>
+#ifdef CONFIG_LS102XA
+#define TSEC_SIZE 0x40000
+#define TSEC_MDIO_OFFSET 0x40000
+#else
#define TSEC_SIZE 0x01000
#define TSEC_MDIO_OFFSET 0x01000
+#endif
#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520)
@@ -128,6 +132,7 @@
#define DMACTRL_INIT_SETTINGS 0x000000c3
#define DMACTRL_GRS 0x00000010
#define DMACTRL_GTS 0x00000008
+#define DMACTRL_LE 0x00008000
#define TSTAT_CLEAR_THALT 0x80000000
#define RSTAT_CLEAR_RHALT 0x00800000