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authorMike Frysinger <vapier@gentoo.org>2008-08-07 15:21:47 -0400
committerMike Frysinger <vapier@gentoo.org>2008-10-23 05:03:50 -0400
commit50f0d211912a648e31aa9123b4665a0444bb8ca9 (patch)
tree5e65f4d336a93e4be0f8a4602cd79827129bea8b
parent3c8798983403cb68a827d7a0d09b1134524a1b7d (diff)
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Blackfin: unify cache handling code
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
-rw-r--r--cpu/blackfin/cpu.c35
-rw-r--r--lib_blackfin/cache.c35
2 files changed, 35 insertions, 35 deletions
diff --git a/cpu/blackfin/cpu.c b/cpu/blackfin/cpu.c
index 0c79932..9efd88e 100644
--- a/cpu/blackfin/cpu.c
+++ b/cpu/blackfin/cpu.c
@@ -14,46 +14,11 @@
#include <asm/blackfin.h>
#include <asm/cplb.h>
#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
#include <asm/mach-common/bits/trace.h>
#include "cpu.h"
#include "serial.h"
-void icache_enable(void)
-{
- bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() | (IMC | ENICPLB));
- SSYNC();
-}
-
-void icache_disable(void)
-{
- bfin_write_IMEM_CONTROL(bfin_read_IMEM_CONTROL() & ~(IMC | ENICPLB));
- SSYNC();
-}
-
-int icache_status(void)
-{
- return bfin_read_IMEM_CONTROL() & ENICPLB;
-}
-
-void dcache_enable(void)
-{
- bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() | (ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
- SSYNC();
-}
-
-void dcache_disable(void)
-{
- bfin_write_DMEM_CONTROL(bfin_read_DMEM_CONTROL() & ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0));
- SSYNC();
-}
-
-int dcache_status(void)
-{
- return bfin_read_DMEM_CONTROL() & ENDCPLB;
-}
-
__attribute__ ((__noreturn__))
void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
{
diff --git a/lib_blackfin/cache.c b/lib_blackfin/cache.c
index c2f6e28..41e2a62 100644
--- a/lib_blackfin/cache.c
+++ b/lib_blackfin/cache.c
@@ -11,6 +11,7 @@
#include <common.h>
#include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
void flush_cache(unsigned long addr, unsigned long size)
{
@@ -24,3 +25,37 @@ void flush_cache(unsigned long addr, unsigned long size)
if (dcache_status())
blackfin_dcache_flush_range((void *)addr, (void *)(addr + size));
}
+
+void icache_enable(void)
+{
+ bfin_write_IMEM_CONTROL(IMC | ENICPLB);
+ SSYNC();
+}
+
+void icache_disable(void)
+{
+ bfin_write_IMEM_CONTROL(0);
+ SSYNC();
+}
+
+int icache_status(void)
+{
+ return bfin_read_IMEM_CONTROL() & ENICPLB;
+}
+
+void dcache_enable(void)
+{
+ bfin_write_DMEM_CONTROL(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
+ SSYNC();
+}
+
+void dcache_disable(void)
+{
+ bfin_write_DMEM_CONTROL(0);
+ SSYNC();
+}
+
+int dcache_status(void)
+{
+ return bfin_read_DMEM_CONTROL() & ENDCPLB;
+}