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authorIra W. Snyder <iws@ovro.caltech.edu>2008-08-22 11:00:14 -0700
committerKim Phillips <kim.phillips@freescale.com>2008-08-25 17:04:30 -0500
commit4ff9aea9d6b5602683a920951ef896996438af62 (patch)
treee8353ef8c49c71121684da3d608d512b63221eb3
parent162338e1fcde231ca4d562e5ebd7859456731691 (diff)
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mpc83xx: add PCISLAVE support to 83XX_GENERIC_PCI setup code
This adds a helper function to unlock the PCI configuration bit, so that any extra PCI setup (such as outbound windows, etc.) can be done after using the 83XX_GENERIC_PCI code to set up the PCI bus. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
-rw-r--r--cpu/mpc83xx/pci.c26
1 files changed, 26 insertions, 0 deletions
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
index adabf7a..c3ec5f8 100644
--- a/cpu/mpc83xx/pci.c
+++ b/cpu/mpc83xx/pci.c
@@ -167,6 +167,32 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot)
pci_init_bus(i, reg[i]);
}
+#ifdef CONFIG_PCISLAVE
+
+#define PCI_FUNCTION_CONFIG 0x44
+#define PCI_FUNCTION_CFG_LOCK 0x20
+
+/*
+ * Unlock the configuration bit so that the host system can begin booting
+ *
+ * This should be used after you have:
+ * 1) Called mpc83xx_pci_init()
+ * 2) Set up your inbound translation windows to the appropriate size
+ */
+void mpc83xx_pcislave_unlock(int bus)
+{
+ struct pci_controller *hose = &pci_hose[bus];
+ u32 dev;
+ u16 reg16;
+
+ /* Unlock configuration lock in PCI function configuration register */
+ dev = PCI_BDF(hose->first_busno, 0, 0);
+ pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, &reg16);
+ reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
+ pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
+}
+#endif
+
#if defined(CONFIG_OF_LIBFDT)
void ft_pci_setup(void *blob, bd_t *bd)
{