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authorFabio Estevam <fabio.estevam@freescale.com>2013-09-30 13:16:52 -0300
committerStefano Babic <sbabic@denx.de>2013-10-31 17:54:03 +0100
commit4867b634b7c0e5ede258b4998fa4b2710e7daacf (patch)
treeab271c06c3561dacd1ce6f9743dcc6f94f1618c0
parent723ec69a6b7eeb3e89d35dcf8fd223702ace6125 (diff)
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ARM: mx5: Enable L2 cache
Enable L2 cache for improving the system performance. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
-rw-r--r--arch/arm/cpu/armv7/mx5/lowlevel_init.S6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 25fadf6..97077fd 100644
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -45,6 +45,12 @@
#endif
mcr 15, 1, r0, c9, c0, 2
+
+ /* enable L2 cache */
+ mrc 15, 0, r0, c1, c0, 1
+ orr r0, r0, #2
+ mcr 15, 0, r0, c1, c0, 1
+
.endm /* init_l2cc */
/* AIPS setup - Only setup MPROTx registers.