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authorWolfgang Denk <wd@denx.de>2010-05-26 22:36:32 +0200
committerWolfgang Denk <wd@denx.de>2010-05-26 22:36:32 +0200
commit45b728cdeef2880ab1e7ebb22eac683900a171a0 (patch)
treecf9426acfae560b6a134495298038a4d88ecd3e7
parentc7da8c19b5f7fd58b5b4b1d247648851af56e1f0 (diff)
parent71bd860cce4493c5def07804723661e75271052b (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu_init.c36
-rw-r--r--arch/powerpc/cpu/mpc83xx/start.S4
2 files changed, 20 insertions, 20 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c
index 75b4522..f3b67ae 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c
@@ -65,16 +65,16 @@ void cpu_init_f (volatile immap_t * im)
{
__be32 acr_mask =
#ifdef CONFIG_SYS_ACR_PIPE_DEP /* Arbiter pipeline depth */
- (ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT) |
+ ACR_PIPE_DEP |
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
- (ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
+ ACR_RPTCNT |
#endif
#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
- (ACR_APARK << ACR_APARK_SHIFT) |
+ ACR_APARK |
#endif
#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
- (ACR_PARKM << ACR_PARKM_SHIFT) |
+ ACR_PARKM |
#endif
0;
__be32 acr_val =
@@ -93,16 +93,16 @@ void cpu_init_f (volatile immap_t * im)
0;
__be32 spcr_mask =
#ifdef CONFIG_SYS_SPCR_OPT /* Optimize transactions between CSB and other dev */
- (SPCR_OPT << SPCR_OPT_SHIFT) |
+ SPCR_OPT |
#endif
#ifdef CONFIG_SYS_SPCR_TSECEP /* all eTSEC's Emergency priority */
- (SPCR_TSECEP << SPCR_TSECEP_SHIFT) |
+ SPCR_TSECEP |
#endif
#ifdef CONFIG_SYS_SPCR_TSEC1EP /* TSEC1 Emergency priority */
- (SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT) |
+ SPCR_TSEC1EP |
#endif
#ifdef CONFIG_SYS_SPCR_TSEC2EP /* TSEC2 Emergency priority */
- (SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT) |
+ SPCR_TSEC2EP |
#endif
0;
__be32 spcr_val =
@@ -121,34 +121,34 @@ void cpu_init_f (volatile immap_t * im)
0;
__be32 sccr_mask =
#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
- (SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
+ SCCR_ENCCM |
#endif
#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
- (SCCR_PCICM << SCCR_PCICM_SHIFT) |
+ SCCR_PCICM |
#endif
#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
- (SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
+ SCCR_TSECCM |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
- (SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
+ SCCR_TSEC1CM |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
- (SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
+ SCCR_TSEC2CM |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
- (SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
+ SCCR_TSEC1ON |
#endif
#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
- (SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
+ SCCR_TSEC2ON |
#endif
#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
- (SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
+ SCCR_USBMPHCM |
#endif
#ifdef CONFIG_SYS_SCCR_USBDRCM /* USB DR clock mode */
- (SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
+ SCCR_USBDRCM |
#endif
#ifdef CONFIG_SYS_SCCR_SATACM /* SATA controller clock mode */
- (SCCR_SATACM << SCCR_SATACM_SHIFT) |
+ SCCR_SATACM |
#endif
0;
__be32 sccr_val =
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index 1b3d618..c7d85a8 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -507,7 +507,7 @@ init_e300_core: /* time t 10 */
lis r3, CONFIG_SYS_IMMR@h
#if defined(CONFIG_WATCHDOG)
- /* Initialise the Wathcdog values and reset it (if req) */
+ /* Initialise the Watchdog values and reset it (if req) */
/*------------------------------------------------------*/
lis r4, CONFIG_SYS_WATCHDOG_VALUE
ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
@@ -520,7 +520,7 @@ init_e300_core: /* time t 10 */
li r4, -0x55C7
sth r4, SWSRR@l(r3)
#else
- /* Disable Wathcdog */
+ /* Disable Watchdog */
/*-------------------*/
lwz r4, SWCRR(r3)
/* Check to see if its enabled for disabling