diff options
| author | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2008-03-06 14:05:53 +0900 |
|---|---|---|
| committer | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2008-03-28 14:16:12 +0900 |
| commit | 3ecff1d70ae93e628fe65b3fe1fc7c9c76cdf99f (patch) | |
| tree | 3a8121e8aecf4ed356ec433bac7b0bbe0a0844bc | |
| parent | c133c1fb0b590662206b0eba70f4478ee0300a9a (diff) | |
| download | u-boot-imx-3ecff1d70ae93e628fe65b3fe1fc7c9c76cdf99f.zip u-boot-imx-3ecff1d70ae93e628fe65b3fe1fc7c9c76cdf99f.tar.gz u-boot-imx-3ecff1d70ae93e628fe65b3fe1fc7c9c76cdf99f.tar.bz2 | |
sh: Fix receive FIFO level register of SH4A
Receive FIFO level register is different in SH4A.
Because register is different, cannot occasionally receive data.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| -rw-r--r-- | drivers/serial/serial_sh.c | 52 |
1 files changed, 30 insertions, 22 deletions
diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index ecb97bf..8ee58a0 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -37,41 +37,45 @@ #define SCFCR (vu_short *)(SCIF_BASE + 0x18) #define SCFDR (vu_short *)(SCIF_BASE + 0x1C) #ifdef CONFIG_CPU_SH7720 /* SH7720 specific */ -#define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ -#define SCFTDR (vu_char *)(SCIF_BASE + 0x20) -#define SCFRDR (vu_char *)(SCIF_BASE + 0x24) +# define SCFSR (vu_short *)(SCIF_BASE + 0x14) /* SCSSR */ +# define SCFTDR (vu_char *)(SCIF_BASE + 0x20) +# define SCFRDR (vu_char *)(SCIF_BASE + 0x24) #else -#define SCFTDR (vu_char *)(SCIF_BASE + 0xC) -#define SCFSR (vu_short *)(SCIF_BASE + 0x10) -#define SCFRDR (vu_char *)(SCIF_BASE + 0x14) +# define SCFTDR (vu_char *)(SCIF_BASE + 0xC) +# define SCFSR (vu_short *)(SCIF_BASE + 0x10) +# define SCFRDR (vu_char *)(SCIF_BASE + 0x14) #endif #if defined(CONFIG_CPU_SH7780) || \ defined(CONFIG_CPU_SH7785) -#define SCRFDR (vu_short *)(SCIF_BASE + 0x20) -#define SCSPTR (vu_short *)(SCIF_BASE + 0x24) -#define SCLSR (vu_short *)(SCIF_BASE + 0x28) -#define SCRER (vu_short *)(SCIF_BASE + 0x2C) -#define LSR_ORER 1 +# define SCRFDR (vu_short *)(SCIF_BASE + 0x20) +# define SCSPTR (vu_short *)(SCIF_BASE + 0x24) +# define SCLSR (vu_short *)(SCIF_BASE + 0x28) +# define SCRER (vu_short *)(SCIF_BASE + 0x2C) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0xFF #elif defined(CONFIG_CPU_SH7750) || \ defined(CONFIG_CPU_SH7722) -#define SCSPTR (vu_short *)(SCIF_BASE + 0x20) -#define SCLSR (vu_short *)(SCIF_BASE + 0x24) -#define LSR_ORER 1 +# define SCSPTR (vu_short *)(SCIF_BASE + 0x20) +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0x1F #elif defined(CONFIG_CPU_SH7720) -#define SCLSR (vu_short *)(SCIF_BASE + 0x24) -#define LSR_ORER 0x0200 +# define SCLSR (vu_short *)(SCIF_BASE + 0x24) +# define LSR_ORER 0x0200 +# define FIFOLEVEL_MASK 0x1F #elif defined(CONFIG_CPU_SH7710) defined(CONFIG_CPU_SH7712) -#define SCLSR SCFSR /* SCSSR */ -#define LSR_ORER 1 +# define SCLSR SCFSR /* SCSSR */ +# define LSR_ORER 1 +# define FIFOLEVEL_MASK 0x1F #endif /* SCBRR register value setting */ #if defined(CONFIG_CPU_SH7720) -#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #else /* Generic SuperH */ -#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) +# define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif #define SCR_RE (1 << 4) @@ -109,12 +113,16 @@ int serial_init (void) static int serial_tx_fifo_level (void) { - return (*SCFDR >> 8) & 0x1F; + return (*SCFDR >> 8) & FIFOLEVEL_MASK; } static int serial_rx_fifo_level (void) { - return (*SCFDR >> 0) & 0x1F; +#if defined(CONFIG_SH4A) + return (*SCRFDR >> 0) & FIFOLEVEL_MASK; +#else + return (*SCFDR >> 0) & FIFOLEVEL_MASK; +#endif } void serial_raw_putc (const char c) |