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authorMarek Vasut <marex@denx.de>2012-03-15 18:33:23 +0000
committerAlbert ARIBAUD <albert.u.boot@aribaud.net>2012-03-29 07:57:08 +0200
commit345cd3584cd90288abd4256678fbfa7d2443bd00 (patch)
tree5b94e43db46a0f6baf1329f4b81843bebb9423d5
parentb3541c1ac93d4e4b786d28ef2f6dc5976a580af5 (diff)
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i.MX28: Enable caches by default
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
-rw-r--r--arch/arm/cpu/arm926ejs/mx28/mx28.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c b/arch/arm/cpu/arm926ejs/mx28/mx28.c
index 9bfd83b..cf6d4e9 100644
--- a/arch/arm/cpu/arm926ejs/mx28/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
@@ -63,6 +63,16 @@ void reset_cpu(ulong ignored)
;
}
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+ icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+ dcache_enable();
+#endif
+}
+
int mx28_wait_mask_set(struct mx28_register_32 *reg, uint32_t mask, int timeout)
{
while (--timeout) {