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authorBo Shen <voice.shen@atmel.com>2013-09-18 15:07:44 +0800
committerAndreas Bießmann <andreas.devel@googlemail.com>2013-11-04 20:32:31 +0100
commit32e4f6bf2e35e99e1742c005e1ede4e0cf5f066c (patch)
tree162f3cf8b80d96149c4a1a8fe337139bd80be12d
parent304db0b38cfb04cfdb05a740d5ef27da06ea98ea (diff)
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net: macb: get DMA bus width from design config register
Get DMA bus width from design config register Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
-rw-r--r--drivers/net/macb.c20
-rw-r--r--drivers/net/macb.h11
2 files changed, 30 insertions, 1 deletions
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index bf3983a..781a272 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -621,6 +621,24 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
return config;
}
+/*
+ * Get the DMA bus width field of the network configuration register that we
+ * should program. We find the width from decoding the design configuration
+ * register to find the maximum supported data bus width.
+ */
+static u32 macb_dbw(struct macb_device *macb)
+{
+ switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
+ case 4:
+ return GEM_BF(DBW, GEM_DBW128);
+ case 2:
+ return GEM_BF(DBW, GEM_DBW64);
+ case 1:
+ default:
+ return GEM_BF(DBW, GEM_DBW32);
+ }
+}
+
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
@@ -665,7 +683,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
*/
if (macb_is_gem(macb)) {
ncfgr = gem_mdc_clk_div(id, macb);
- ncfgr |= GEM_BF(DBW, 1);
+ ncfgr |= macb_dbw(macb);
} else {
ncfgr = macb_mdc_clk_div(id, macb);
}
diff --git a/drivers/net/macb.h b/drivers/net/macb.h
index de5214f..06f7c66 100644
--- a/drivers/net/macb.h
+++ b/drivers/net/macb.h
@@ -58,6 +58,9 @@
#define MACB_WOL 0x00c4
#define MACB_MID 0x00fc
+/* GEM specific register offsets */
+#define GEM_DCFG1 0x0280
+
/* Bitfields in NCR */
#define MACB_LB_OFFSET 0
#define MACB_LB_SIZE 1
@@ -242,6 +245,14 @@
#define MACB_IDNUM_SIZE 16
/* Bitfields in DCFG1 */
+#define GEM_DBWDEF_OFFSET 25
+#define GEM_DBWDEF_SIZE 3
+
+/* constants for data bus width */
+#define GEM_DBW32 0
+#define GEM_DBW64 1
+#define GEM_DBW128 2
+
/* Constants for CLK */
#define MACB_CLK_DIV8 0
#define MACB_CLK_DIV16 1