summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorWolfgang Denk <wd@denx.de>2009-10-12 23:40:27 +0200
committerWolfgang Denk <wd@denx.de>2009-10-12 23:40:27 +0200
commit14abfe361b3ed23b02f564e2f5d663e158cd5799 (patch)
tree76ccf4f0ce3bb2d8c0fda116ee3d0e10de262af5
parent285870f75378aca41c5063e4358ad93bf3014fd8 (diff)
parentbe2254423b86572841aa70ff05d20933d1b49823 (diff)
downloadu-boot-imx-14abfe361b3ed23b02f564e2f5d663e158cd5799.zip
u-boot-imx-14abfe361b3ed23b02f564e2f5d663e158cd5799.tar.gz
u-boot-imx-14abfe361b3ed23b02f564e2f5d663e158cd5799.tar.bz2
Merge branch 'master' of /home/wd/git/u-boot/custodians
-rw-r--r--doc/README.bitbangMII56
-rw-r--r--drivers/net/phy/miiphybb.c346
-rw-r--r--include/configs/ISPAN.h4
-rw-r--r--include/configs/MPC8260ADS.h3
-rw-r--r--include/configs/MPC8266ADS.h4
-rw-r--r--include/configs/MPC8560ADS.h4
-rw-r--r--include/configs/Rattler.h4
-rw-r--r--include/configs/SBC8540.h4
-rw-r--r--include/configs/TQM8272.h3
-rw-r--r--include/configs/VoVPN-GW.h5
-rw-r--r--include/configs/ZPC1900.h4
-rw-r--r--include/configs/ep8248.h1
-rw-r--r--include/configs/ep82xxm.h1
-rw-r--r--include/configs/gw8260.h5
-rw-r--r--include/configs/hymod.h12
-rw-r--r--include/configs/muas3001.h4
-rw-r--r--include/configs/ppmc8260.h4
-rw-r--r--include/configs/sacsng.h4
-rw-r--r--include/configs/sbc8260.h4
-rw-r--r--include/configs/sbc8560.h4
-rw-r--r--include/miiphy.h25
-rw-r--r--lib_arm/board.c7
-rw-r--r--lib_avr32/board.c7
-rw-r--r--lib_blackfin/board.c7
-rw-r--r--lib_i386/board.c9
-rw-r--r--lib_m68k/board.c7
-rw-r--r--lib_mips/board.c7
-rw-r--r--lib_ppc/board.c7
-rw-r--r--lib_sh/board.c7
-rw-r--r--lib_sparc/board.c7
30 files changed, 460 insertions, 106 deletions
diff --git a/doc/README.bitbangMII b/doc/README.bitbangMII
new file mode 100644
index 0000000..edd0856
--- /dev/null
+++ b/doc/README.bitbangMII
@@ -0,0 +1,56 @@
+This patch rewrites the miiphybb ( Bit-banged MII bus driver ) in order to
+support an arbitrary number of mii buses. This feature is useful when your
+board uses different mii buses for different phys and all (or a part) of these
+buses are implemented via bit-banging mode.
+
+The driver requires that the following macros should be defined into the board
+configuration file:
+
+CONFIG_BITBANGMII - Enable the miiphybb driver
+CONFIG_BITBANGMII_MULTI - Enable the multi bus support
+
+If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs
+to define at least the following macros:
+
+MII_INIT - Generic code to enable the MII bus (optional)
+MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional)
+MDIO_ACTIVE - Activate the MDIO pin as out pin
+MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
+MDIO_READ - Read the MDIO pin
+MDIO(v) - Write v on the MDIO pin
+MDC_DECLARE - Declaration needed to access to the MDC pin (optional)
+MDC(v) - Write v on the MDC pin
+
+The previous macros make the driver compatible with the previous version
+(that didn't support the multi-bus).
+
+When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill
+the bb_miiphy_buses[] array with a record for each required bus and declare
+the bb_miiphy_buses_num variable with the number of mii buses.
+The record (struct bb_miiphy_bus) has the following fields/callbacks (see
+miiphy.h for details):
+
+char name[] - The symbolic name that must be equal to the MII bus
+ registered name
+int (*init)() - Initialization function called at startup time (just
+ before the Ethernet initialization)
+int (*mdio_active)() - Activate the MDIO pin as output
+int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin
+int (*set_mdio)() - Write the MDIO pin
+int (*get_mdio)() - Read the MDIO pin
+int (*set_mdc)() - Write the MDC pin
+int (*delay)() - Delay function
+void *priv - Private data used by board specific code
+
+The board code will look like:
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+ { .name = "miibus#1", .init = b1_init, .mdio_active = b1_mdio_active, ... },
+ { .name = "miibus#2", .init = b2_init, .mdio_active = b2_mdio_active, ... },
+ ...
+};
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+ sizeof(bb_miiphy_buses[0]);
+
+2009 Industrie Dial Face S.p.A.
+ Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c
index b77c917..44c45fa 100644
--- a/drivers/net/phy/miiphybb.c
+++ b/drivers/net/phy/miiphybb.c
@@ -1,4 +1,7 @@
/*
+ * (C) Copyright 2009 Industrie Dial Face S.p.A.
+ * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
+ *
* (C) Copyright 2001
* Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
*
@@ -29,18 +32,144 @@
#include <common.h>
#include <ioports.h>
#include <ppc_asm.tmpl>
+#include <miiphy.h>
+
+#define BB_MII_RELOCATE(v,off) (v += (v?off:0))
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_BITBANGMII_MULTI
+
+/*
+ * If CONFIG_BITBANGMII_MULTI is not defined we use a
+ * compatibility layer with the previous miiphybb implementation
+ * based on macros usage.
+ *
+ */
+static int bb_mii_init_wrap(struct bb_miiphy_bus *bus)
+{
+#ifdef MII_INIT
+ MII_INIT;
+#endif
+ return 0;
+}
+
+static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus)
+{
+#ifdef MDIO_DECLARE
+ MDIO_DECLARE;
+#endif
+ MDIO_ACTIVE;
+ return 0;
+}
+
+static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus)
+{
+#ifdef MDIO_DECLARE
+ MDIO_DECLARE;
+#endif
+ MDIO_TRISTATE;
+ return 0;
+}
+
+static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v)
+{
+#ifdef MDIO_DECLARE
+ MDIO_DECLARE;
+#endif
+ MDIO(v);
+ return 0;
+}
+
+static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v)
+{
+#ifdef MDIO_DECLARE
+ MDIO_DECLARE;
+#endif
+ *v = MDIO_READ;
+ return 0;
+}
+
+static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v)
+{
+#ifdef MDC_DECLARE
+ MDC_DECLARE;
+#endif
+ MDC(v);
+ return 0;
+}
+
+static int bb_delay_wrap(struct bb_miiphy_bus *bus)
+{
+ MIIDELAY;
+ return 0;
+}
+
+struct bb_miiphy_bus bb_miiphy_buses[] = {
+ {
+ .name = BB_MII_DEVNAME,
+ .init = bb_mii_init_wrap,
+ .mdio_active = bb_mdio_active_wrap,
+ .mdio_tristate = bb_mdio_tristate_wrap,
+ .set_mdio = bb_set_mdio_wrap,
+ .get_mdio = bb_get_mdio_wrap,
+ .set_mdc = bb_set_mdc_wrap,
+ .delay = bb_delay_wrap,
+ }
+};
+
+int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) /
+ sizeof(bb_miiphy_buses[0]);
+#endif
+
+void bb_miiphy_init(void)
+{
+ int i;
+
+ for (i = 0; i < bb_miiphy_buses_num; i++) {
+#if !defined(CONFIG_RELOC_FIXUP_WORKS)
+ /* Relocate the hook pointers*/
+ BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off);
+ BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off);
+ BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off);
+ BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off);
+ BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off);
+ BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off);
+ BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off);
+#endif
+ if (bb_miiphy_buses[i].init != NULL) {
+ bb_miiphy_buses[i].init(&bb_miiphy_buses[i]);
+ }
+ }
+}
+
+static inline struct bb_miiphy_bus *bb_miiphy_getbus(char *devname)
+{
+#ifdef CONFIG_BITBANGMII_MULTI
+ int i;
+
+ /* Search the correct bus */
+ for (i = 0; i < bb_miiphy_buses_num; i++) {
+ if (!strcmp(bb_miiphy_buses[i].name, devname)) {
+ return &bb_miiphy_buses[i];
+ }
+ }
+ return NULL;
+#else
+ /* We have just one bitbanging bus */
+ return &bb_miiphy_buses[0];
+#endif
+}
/*****************************************************************************
*
* Utility to send the preamble, address, and register (common to read
* and write).
*/
-static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
+static void miiphy_pre(struct bb_miiphy_bus *bus, char read,
+ unsigned char addr, unsigned char reg)
{
- int j; /* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
- volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
-#endif
+ int j;
/*
* Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
@@ -50,67 +179,66 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
* but it is safer and will be much more robust.
*/
- MDIO_ACTIVE;
- MDIO (1);
+ bus->mdio_active(bus);
+ bus->set_mdio(bus, 1);
for (j = 0; j < 32; j++) {
- MDC (0);
- MIIDELAY;
- MDC (1);
- MIIDELAY;
+ bus->set_mdc(bus, 0);
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
}
/* send the start bit (01) and the read opcode (10) or write (10) */
- MDC (0);
- MDIO (0);
- MIIDELAY;
- MDC (1);
- MIIDELAY;
- MDC (0);
- MDIO (1);
- MIIDELAY;
- MDC (1);
- MIIDELAY;
- MDC (0);
- MDIO (read);
- MIIDELAY;
- MDC (1);
- MIIDELAY;
- MDC (0);
- MDIO (!read);
- MIIDELAY;
- MDC (1);
- MIIDELAY;
+ bus->set_mdc(bus, 0);
+ bus->set_mdio(bus, 0);
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
+ bus->set_mdc(bus, 0);
+ bus->set_mdio(bus, 1);
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
+ bus->set_mdc(bus, 0);
+ bus->set_mdio(bus, read);
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
+ bus->set_mdc(bus, 0);
+ bus->set_mdio(bus, !read);
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
/* send the PHY address */
for (j = 0; j < 5; j++) {
- MDC (0);
+ bus->set_mdc(bus, 0);
if ((addr & 0x10) == 0) {
- MDIO (0);
+ bus->set_mdio(bus, 0);
} else {
- MDIO (1);
+ bus->set_mdio(bus, 1);
}
- MIIDELAY;
- MDC (1);
- MIIDELAY;
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
addr <<= 1;
}
/* send the register address */
for (j = 0; j < 5; j++) {
- MDC (0);
+ bus->set_mdc(bus, 0);
if ((reg & 0x10) == 0) {
- MDIO (0);
+ bus->set_mdio(bus, 0);
} else {
- MDIO (1);
+ bus->set_mdio(bus, 1);
}
- MIIDELAY;
- MDC (1);
- MIIDELAY;
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
reg <<= 1;
}
}
-
/*****************************************************************************
*
* Read a MII PHY register.
@@ -118,63 +246,69 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg)
* Returns:
* 0 on success
*/
-int bb_miiphy_read (char *devname, unsigned char addr,
- unsigned char reg, unsigned short *value)
+int bb_miiphy_read(char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
{
- short rdreg; /* register working value */
- int j; /* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
- volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
-#endif
+ short rdreg; /* register working value */
+ int v;
+ int j; /* counter */
+ struct bb_miiphy_bus *bus;
+
+ bus = bb_miiphy_getbus(devname);
+ if (bus == NULL) {
+ return -1;
+ }
if (value == NULL) {
puts("NULL value pointer\n");
- return (-1);
+ return -1;
}
- miiphy_pre (1, addr, reg);
+ miiphy_pre (bus, 1, addr, reg);
/* tri-state our MDIO I/O pin so we can read */
- MDC (0);
- MDIO_TRISTATE;
- MIIDELAY;
- MDC (1);
- MIIDELAY;
+ bus->set_mdc(bus, 0);
+ bus->mdio_tristate(bus);
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
/* check the turnaround bit: the PHY should be driving it to zero */
- if (MDIO_READ != 0) {
+ bus->get_mdio(bus, &v);
+ if (v != 0) {
/* puts ("PHY didn't drive TA low\n"); */
for (j = 0; j < 32; j++) {
- MDC (0);
- MIIDELAY;
- MDC (1);
- MIIDELAY;
+ bus->set_mdc(bus, 0);
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
}
/* There is no PHY, set value to 0xFFFF and return */
*value = 0xFFFF;
- return (-1);
+ return -1;
}
- MDC (0);
- MIIDELAY;
+ bus->set_mdc(bus, 0);
+ bus->delay(bus);
/* read 16 bits of register data, MSB first */
rdreg = 0;
for (j = 0; j < 16; j++) {
- MDC (1);
- MIIDELAY;
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
rdreg <<= 1;
- rdreg |= MDIO_READ;
- MDC (0);
- MIIDELAY;
+ bus->get_mdio(bus, &v);
+ rdreg |= (v & 0x1);
+ bus->set_mdc(bus, 0);
+ bus->delay(bus);
}
- MDC (1);
- MIIDELAY;
- MDC (0);
- MIIDELAY;
- MDC (1);
- MIIDELAY;
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
+ bus->set_mdc(bus, 0);
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
*value = rdreg;
@@ -194,49 +328,53 @@ int bb_miiphy_read (char *devname, unsigned char addr,
* 0 on success
*/
int bb_miiphy_write (char *devname, unsigned char addr,
- unsigned char reg, unsigned short value)
+ unsigned char reg, unsigned short value)
{
+ struct bb_miiphy_bus *bus;
int j; /* counter */
-#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM))
- volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT);
-#endif
- miiphy_pre (0, addr, reg);
+ bus = bb_miiphy_getbus(devname);
+ if (bus == NULL) {
+ /* Bus not found! */
+ return -1;
+ }
+
+ miiphy_pre (bus, 0, addr, reg);
/* send the turnaround (10) */
- MDC (0);
- MDIO (1);
- MIIDELAY;
- MDC (1);
- MIIDELAY;
- MDC (0);
- MDIO (0);
- MIIDELAY;
- MDC (1);
- MIIDELAY;
+ bus->set_mdc(bus, 0);
+ bus->set_mdio(bus, 1);
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
+ bus->set_mdc(bus, 0);
+ bus->set_mdio(bus, 0);
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
/* write 16 bits of register data, MSB first */
for (j = 0; j < 16; j++) {
- MDC (0);
+ bus->set_mdc(bus, 0);
if ((value & 0x00008000) == 0) {
- MDIO (0);
+ bus->set_mdio(bus, 0);
} else {
- MDIO (1);
+ bus->set_mdio(bus, 1);
}
- MIIDELAY;
- MDC (1);
- MIIDELAY;
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
value <<= 1;
}
/*
* Tri-state the MDIO line.
*/
- MDIO_TRISTATE;
- MDC (0);
- MIIDELAY;
- MDC (1);
- MIIDELAY;
+ bus->mdio_tristate(bus);
+ bus->set_mdc(bus, 0);
+ bus->delay(bus);
+ bus->set_mdc(bus, 1);
+ bus->delay(bus);
return 0;
-}
+} \ No newline at end of file
diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h
index 6eb466a..c0b1d86 100644
--- a/include/configs/ISPAN.h
+++ b/include/configs/ISPAN.h
@@ -84,6 +84,10 @@
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 3 /* Port D */
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
+
#define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */
#define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */
diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h
index 39b8b8f..ffd37fd 100644
--- a/include/configs/MPC8260ADS.h
+++ b/include/configs/MPC8260ADS.h
@@ -150,6 +150,9 @@
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 2 /* Port C */
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */
diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h
index b0162c3..55d77f8 100644
--- a/include/configs/MPC8266ADS.h
+++ b/include/configs/MPC8266ADS.h
@@ -96,6 +96,10 @@
* Port pins used for bit-banged MII communictions (if applicable).
*/
#define MDIO_PORT 2 /* Port C */
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
+
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 8ddce5c..df59aca 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -363,6 +363,10 @@
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 2 /* Port C */
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
+
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h
index 5b6f271..e630afe 100644
--- a/include/configs/Rattler.h
+++ b/include/configs/Rattler.h
@@ -103,6 +103,10 @@
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 2 /* Port C */
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
+
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h
index 7cde39b..1989e5a 100644
--- a/include/configs/SBC8540.h
+++ b/include/configs/SBC8540.h
@@ -290,6 +290,10 @@
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 2 /* Port C */
+ #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+ #define MDC_DECLARE MDIO_DECLARE
+
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h
index 6c462af..6eaa61d 100644
--- a/include/configs/TQM8272.h
+++ b/include/configs/TQM8272.h
@@ -219,6 +219,9 @@
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 2 /* Port C */
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
#if STK82xx_150
#define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */
diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h
index b2d75e3..3614184 100644
--- a/include/configs/VoVPN-GW.h
+++ b/include/configs/VoVPN-GW.h
@@ -124,6 +124,11 @@
#define CONFIG_BITBANGMII
#define MDIO_PORT 1 /* Port B */
+
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
+
#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PB18 */
#define CONFIG_SYS_MDC_PIN 0x00001000 /* PB19 */
#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h
index 9cda3f9..8ae765c 100644
--- a/include/configs/ZPC1900.h
+++ b/include/configs/ZPC1900.h
@@ -86,6 +86,10 @@
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 2 /* Port C */
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
+
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h
index cb4185a..a738425 100644
--- a/include/configs/ep8248.h
+++ b/include/configs/ep8248.h
@@ -92,6 +92,7 @@
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 0 /* Not used - implemented in BCSR */
+
#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h
index 239ff67..c737f10 100644
--- a/include/configs/ep82xxm.h
+++ b/include/configs/ep82xxm.h
@@ -85,6 +85,7 @@
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 0 /* Not used - implemented in BCSR */
+
#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h
index 53a001d..9ed3846 100644
--- a/include/configs/gw8260.h
+++ b/include/configs/gw8260.h
@@ -212,6 +212,11 @@
* Port pins used for bit-banged MII communictions (if applicable).
*/
#define MDIO_PORT 2 /* Port C */
+
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
+
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
diff --git a/include/configs/hymod.h b/include/configs/hymod.h
index 284672b..5a282ff 100644
--- a/include/configs/hymod.h
+++ b/include/configs/hymod.h
@@ -93,6 +93,10 @@
# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
# define MDIO_PORT 0 /* Port A */
+# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+# define MDC_DECLARE MDIO_DECLARE
+
# define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */
# define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */
@@ -110,6 +114,10 @@
# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
# define MDIO_PORT 0 /* Port A */
+# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+# define MDC_DECLARE MDIO_DECLARE
+
# define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */
# define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */
@@ -127,6 +135,10 @@
# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
# define MDIO_PORT 0 /* Port A */
+# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+# define MDC_DECLARE MDIO_DECLARE
+
# define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */
# define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */
diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h
index c94daa3..43f46bf 100644
--- a/include/configs/muas3001.h
+++ b/include/configs/muas3001.h
@@ -101,6 +101,10 @@
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 0 /* Port A */
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
+
#define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */
#define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */
diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h
index ff7d614..f387601 100644
--- a/include/configs/ppmc8260.h
+++ b/include/configs/ppmc8260.h
@@ -182,6 +182,10 @@
* Port pins used for bit-banged MII communictions (if applicable).
*/
#define MDIO_PORT 2 /* Port C */
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
+
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index 0ab6fc3..b0198aa 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -179,6 +179,10 @@
*/
#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
+
#define MDIO_ACTIVE (iop->pdir |= 0x40000000)
#define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
#define MDIO_READ ((iop->pdat & 0x40000000) != 0)
diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h
index 26ed557..3fa80a8 100644
--- a/include/configs/sbc8260.h
+++ b/include/configs/sbc8260.h
@@ -201,6 +201,10 @@
* Port pins used for bit-banged MII communictions (if applicable).
*/
#define MDIO_PORT 2 /* Port C */
+#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+#define MDC_DECLARE MDIO_DECLARE
+
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h
index a6b15f7..dab4f80 100644
--- a/include/configs/sbc8560.h
+++ b/include/configs/sbc8560.h
@@ -293,6 +293,10 @@
* GPIO pins used for bit-banged MII communications
*/
#define MDIO_PORT 2 /* Port C */
+ #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
+ (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
+ #define MDC_DECLARE MDIO_DECLARE
+
#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
diff --git a/include/miiphy.h b/include/miiphy.h
index fa33ec7..5362125 100644
--- a/include/miiphy.h
+++ b/include/miiphy.h
@@ -19,6 +19,8 @@
|
| COPYRIGHT I B M CORPORATION 1999
| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
+|
+| Additions (C) Copyright 2009 Industrie Dial Face S.p.A.
+----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------+
|
@@ -61,12 +63,33 @@ char *miiphy_get_current_dev (void);
void miiphy_listdev (void);
-#define BB_MII_DEVNAME "bbmii"
+#ifdef CONFIG_BITBANGMII
+
+#define BB_MII_DEVNAME "bb_miiphy"
+
+struct bb_miiphy_bus {
+ char name[NAMESIZE];
+ int (*init)(struct bb_miiphy_bus *bus);
+ int (*mdio_active)(struct bb_miiphy_bus *bus);
+ int (*mdio_tristate)(struct bb_miiphy_bus *bus);
+ int (*set_mdio)(struct bb_miiphy_bus *bus, int v);
+ int (*get_mdio)(struct bb_miiphy_bus *bus, int *v);
+ int (*set_mdc)(struct bb_miiphy_bus *bus, int v);
+ int (*delay)(struct bb_miiphy_bus *bus);
+#ifdef CONFIG_BITBANGMII_MULTI
+ void *priv;
+#endif
+};
+
+extern struct bb_miiphy_bus bb_miiphy_buses[];
+extern int bb_miiphy_buses_num;
+void bb_miiphy_init (void);
int bb_miiphy_read (char *devname, unsigned char addr,
unsigned char reg, unsigned short *value);
int bb_miiphy_write (char *devname, unsigned char addr,
unsigned char reg, unsigned short value);
+#endif
/* phy seed setup */
#define AUTO 99
diff --git a/lib_arm/board.c b/lib_arm/board.c
index a0e56d5..5e3d7f6 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -50,6 +50,10 @@
#include <onenand_uboot.h>
#include <mmc.h>
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+
#ifdef CONFIG_DRIVER_SMC91111
#include "../drivers/net/smc91111.h"
#endif
@@ -417,6 +421,9 @@ extern void davinci_eth_set_mac_addr (const u_int8_t *addr);
mmc_initialize (gd->bd);
#endif
+#ifdef CONFIG_BITBANGMII
+ bb_miiphy_init();
+#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts ("Net: ");
diff --git a/lib_avr32/board.c b/lib_avr32/board.c
index 29999d8..917ed6c 100644
--- a/lib_avr32/board.c
+++ b/lib_avr32/board.c
@@ -27,6 +27,10 @@
#include <version.h>
#include <net.h>
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+
#include <asm/initcalls.h>
#include <asm/sections.h>
@@ -337,6 +341,9 @@ void board_init_r(gd_t *new_gd, ulong dest_addr)
if (s)
load_addr = simple_strtoul(s, NULL, 16);
+#ifdef CONFIG_BITBANGMII
+ bb_miiphy_init();
+#endif
#if defined(CONFIG_CMD_NET)
s = getenv("bootfile");
if (s)
diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c
index 1053f69..3670d2c 100644
--- a/lib_blackfin/board.c
+++ b/lib_blackfin/board.c
@@ -26,6 +26,10 @@
#include <nand.h> /* cannot even include nand.h if it isnt configured */
#endif
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+
#if defined(CONFIG_POST)
#include <post.h>
int post_flag;
@@ -270,6 +274,9 @@ void board_init_f(ulong bootflag)
static void board_net_init_r(bd_t *bd)
{
+#ifdef CONFIG_BITBANGMII
+ bb_miiphy_init();
+#endif
#ifdef CONFIG_CMD_NET
uchar enetaddr[6];
char *s;
diff --git a/lib_i386/board.c b/lib_i386/board.c
index 0262b5e..12ca20f 100644
--- a/lib_i386/board.c
+++ b/lib_i386/board.c
@@ -1,6 +1,6 @@
/*
* (C) Copyright 2002
- * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
+ * Daniel Engstr�m, Omicron Ceti AB, daniel@omicron.se
*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
@@ -39,6 +39,10 @@
#include <ide.h>
#include <asm/u-boot-i386.h>
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
extern long _i386boot_start;
@@ -351,6 +355,9 @@ void start_i386boot (void)
doc_init();
#endif
+#ifdef CONFIG_BITBANGMII
+ bb_miiphy_init();
+#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
WATCHDOG_RESET();
diff --git a/lib_m68k/board.c b/lib_m68k/board.c
index 3d88530..732023d 100644
--- a/lib_m68k/board.c
+++ b/lib_m68k/board.c
@@ -63,6 +63,10 @@
#include <spi.h>
#endif
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+
#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -630,6 +634,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
nand_init(); /* go init the NAND */
#endif
+#ifdef CONFIG_BITBANGMII
+ bb_miiphy_init();
+#endif
#if defined(CONFIG_CMD_NET)
WATCHDOG_RESET();
#if defined(FEC_ENET)
diff --git a/lib_mips/board.c b/lib_mips/board.c
index f62a46a..b2d113e 100644
--- a/lib_mips/board.c
+++ b/lib_mips/board.c
@@ -33,6 +33,10 @@
#include <onenand_uboot.h>
#include <spi.h>
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
#if ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \
@@ -407,6 +411,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
misc_init_r ();
#endif
+#ifdef CONFIG_BITBANGMII
+ bb_miiphy_init();
+#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
puts ("Net: ");
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 8b8ddb5..796d002 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -83,6 +83,10 @@
#include <asm/mp.h>
#endif
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+
#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
extern int update_flash_size (int flash_size);
#endif
@@ -942,6 +946,9 @@ void board_init_r (gd_t *id, ulong dest_addr)
doc_init ();
#endif
+#ifdef CONFIG_BITBANGMII
+ bb_miiphy_init();
+#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
WATCHDOG_RESET ();
diff --git a/lib_sh/board.c b/lib_sh/board.c
index 5d61f0d..5ed40e9 100644
--- a/lib_sh/board.c
+++ b/lib_sh/board.c
@@ -28,6 +28,10 @@
#include <net.h>
#include <environment.h>
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+
extern void malloc_bin_reloc (void);
extern int cpu_init(void);
extern int board_init(void);
@@ -178,6 +182,9 @@ void sh_generic_init(void)
#endif /* CONFIG_WATCHDOG*/
+#ifdef CONFIG_BITBANGMII
+ bb_miiphy_init();
+#endif
#if defined(CONFIG_CMD_NET)
{
char *s;
diff --git a/lib_sparc/board.c b/lib_sparc/board.c
index 6aadb56..11eea60 100644
--- a/lib_sparc/board.c
+++ b/lib_sparc/board.c
@@ -49,6 +49,10 @@
#include <ambapp.h>
#endif
+#ifdef CONFIG_BITBANGMII
+#include <miiphy.h>
+#endif
+
DECLARE_GLOBAL_DATA_PTR;
/* Debug options
@@ -405,6 +409,9 @@ void board_init_f(ulong bootflag)
doc_init();
#endif
+#ifdef CONFIG_BITBANGMII
+ bb_miiphy_init();
+#endif
#if defined(CONFIG_CMD_NET)
#if defined(CONFIG_NET_MULTI)
WATCHDOG_RESET();