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authorAlison Wang <b18965@freescale.com>2014-10-17 15:26:36 +0800
committerYork Sun <yorksun@freescale.com>2014-11-24 09:27:24 -0800
commit0ab172353e14dbdb7278755de6feae3fc4b54c2f (patch)
tree2e18ee3aec0b22ec380428433878a5ccde771785
parent5175a2885fbb47e4836dcb8ad0ad2214e9b0b3b5 (diff)
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arm: ls102xa: Select ge2_clk125 for eTSEC clock muxing
EC1 pins in RCW can be selected as RGMII1, GPIO3, CAN1/2, FTM1 or SAI1/2. There is a bug that EC3 RGMII could not work when selecting EC1 as other functionality except RGMII. The workaround is to select ge2_clk125 for eTSEC clock muxing in register SCFG_ETSECCMCR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
-rw-r--r--board/freescale/ls1021aqds/ls1021aqds.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 913dda9..d64b24c 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -141,6 +141,7 @@ int board_early_init_f(void)
#ifdef CONFIG_TSEC_ENET
out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
+ out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
#endif
#ifdef CONFIG_FSL_IFC