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authorDave Liu <daveliu@freescale.com>2009-12-16 10:24:36 -0600
committerKumar Gala <galak@kernel.crashing.org>2010-01-05 13:49:10 -0600
commit0a71c92c7e1e565111cb34cd389a21ec500ca5c1 (patch)
treeabee130bc9075de43eb494b30e102a907ffda992
parentc4ca10f1db36c3ce649c656dec14f7aab644dd86 (diff)
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fsl-ddr: Fix power-down timing settings
1. TIMING_CFG_0[ACT_PD_EXIT] was set to 6 clocks, but It should be set to tXP parameter, tXP=max(3CK, 7.5ns) 2. TIMING_CFG_0[PRE_PD_EXIT] was set to 6 clocks, but It should be set to tXP (if MR0[A12]=1) else to tXPDLL parameter We are setting the mode register MR0[A12]='1' Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r--cpu/mpc8xxx/ddr/ctrl_regs.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c
index 2505041..a92f1a3 100644
--- a/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -188,12 +188,13 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
* The DDR3 spec has not tXARD,
* we use the tXP instead of it.
* tXP=max(3nCK, 7.5ns) for DDR3.
- * we use the tXP=6
* spec has not the tAXPD, we use
* tAXPD=8, need design to confirm.
*/
- act_pd_exit_mclk = 6;
- pre_pd_exit_mclk = 6;
+ int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
+ act_pd_exit_mclk = picos_to_mclk(tXP);
+ /* Mode register MR0[A12] is '1' - fast exit */
+ pre_pd_exit_mclk = act_pd_exit_mclk;
taxpd_mclk = 8;
tmrd_mclk = 4;
#else /* CONFIG_FSL_DDR2 */