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| author | Ye.Li <B37916@freescale.com> | 2014-06-12 16:28:38 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-06-17 11:14:01 +0800 |
| commit | bfc7a914724643beb327d6b9412afa468ead81ec (patch) | |
| tree | 72abf6b9434d5e83c2f80ebf784fe7814e663f4e | |
| parent | d94fe28bb7687a7e062865f36b812cfa73b9dfc8 (diff) | |
| download | u-boot-imx-bfc7a914724643beb327d6b9412afa468ead81ec.zip u-boot-imx-bfc7a914724643beb327d6b9412afa468ead81ec.tar.gz u-boot-imx-bfc7a914724643beb327d6b9412afa468ead81ec.tar.bz2 | |
ENGR00315894-65 iMX6SX:SABRESD Add RDC settings to BSP
According to the SRS, in the M4 CAN demo, the GPIO group1 will be
shared between A9 and M4. At A9 side, the pins 0, 1, 2, 3 are used.
M4 also uses one pin in its application.
To synchronize the registers setttings of GPIO1, must enable RDC
and RDC semaphore on the GPIO1.
Signed-off-by: Ye.Li <B37916@freescale.com>
| -rw-r--r-- | board/freescale/mx6sxsabresd/mx6sxsabresd.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 810d1dc..3f098f4 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -22,6 +22,10 @@ #include <i2c.h> #include <asm/imx-common/mxc_i2c.h> #endif +#ifdef CONFIG_MXC_RDC +#include <asm/imx-common/rdc-sema.h> +#include <asm/arch/imx-rdc.h> +#endif DECLARE_GLOBAL_DATA_PTR; @@ -539,8 +543,18 @@ void ldo_mode_set(int ldo_bypass) #endif #endif +#ifdef CONFIG_MXC_RDC +static rdc_peri_cfg_t const shared_resources[] = { + (RDC_PER_GPIO1 | RDC_DOMAIN(0) | RDC_DOMAIN(1)), +}; +#endif + int board_early_init_f(void) { +#ifdef CONFIG_MXC_RDC + imx_rdc_setup_peripherals(shared_resources, ARRAY_SIZE(shared_resources)); +#endif + setup_iomux_uart(); return 0; } |