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| author | Ye.Li <B37916@freescale.com> | 2014-06-10 16:53:58 +0800 |
|---|---|---|
| committer | Ye.Li <B37916@freescale.com> | 2014-06-17 11:13:53 +0800 |
| commit | b18346b6b48dc23f1095208b4157164c001ad9e5 (patch) | |
| tree | f5f57e07bfbf3d7732c7b43b7eaa375501e8170e | |
| parent | 070c01291e25f4f16cd0df971ddb6c67a0a57152 (diff) | |
| download | u-boot-imx-b18346b6b48dc23f1095208b4157164c001ad9e5.zip u-boot-imx-b18346b6b48dc23f1095208b4157164c001ad9e5.tar.gz u-boot-imx-b18346b6b48dc23f1095208b4157164c001ad9e5.tar.bz2 | |
ENGR00315894-49 SD/MMC: Update fsl_esdhc driver for iMX6SX
The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0
on iMX6SX. So the fsl_esdhc driver must update to set the register,
otherwise no state can be detected.
Signed-off-by: Ye.Li <B37916@freescale.com>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 6ca61c7..5e04cde 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -23,6 +23,11 @@ DECLARE_GLOBAL_DATA_PTR; +#define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \ + IRQSTATEN_CINT | \ + IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \ + IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | IRQSTATEN_DEBE) + struct fsl_esdhc { uint dsaddr; /* SDMA system address register */ uint blkattr; /* Block attributes register */ @@ -510,8 +515,15 @@ static int esdhc_init(struct mmc *mmc) /* Set the initial clock speed */ mmc_set_clock(mmc, 400000); +#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO + /* Enable the BRR and BWR bits in IRQSTAT */ + esdhc_clrbits32(®s->irqstaten, IRQSTATEN_DINT); + esdhc_setbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); +#else /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); + esdhc_setbits32(®s->irqstaten, IRQSTATEN_DINT); +#endif /* Put the PROCTL reg back to the default */ esdhc_write32(®s->proctl, PROCTL_INIT); @@ -576,6 +588,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN | SYSCTL_IPGEN | SYSCTL_CKEN); + writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten); memset(&cfg->cfg, 0, sizeof(cfg->cfg)); voltage_caps = 0; |