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| author | Mike Frysinger <vapier@gentoo.org> | 2010-08-11 17:54:00 -0400 |
|---|---|---|
| committer | Remy Bohmer <linux@bohmer.net> | 2010-09-20 21:56:42 +0200 |
| commit | 70fccb3f2469f5cfd75ad17c6e452a382fbabbcf (patch) | |
| tree | 3d22c5b0a4b114c47d552d74b21494a36c7b0fa2 | |
| parent | ff377b1c0e891569b6da13629090aad7c38175e0 (diff) | |
| download | u-boot-imx-70fccb3f2469f5cfd75ad17c6e452a382fbabbcf.zip u-boot-imx-70fccb3f2469f5cfd75ad17c6e452a382fbabbcf.tar.gz u-boot-imx-70fccb3f2469f5cfd75ad17c6e452a382fbabbcf.tar.bz2 | |
usb: musb: stub out MUSB_TXCSR_MODE for Blackfin parts
The MUSB_TXCSR_MODE register setting isn't supported on Blackfin musb
parts, so stub it out to 0. This matches Linux behavior.
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| -rw-r--r-- | drivers/usb/musb/musb_core.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index 4771876..8f73876 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -369,6 +369,8 @@ extern void read_fifo(u8 ep, u32 length, void *fifo_data); # define readb(addr) (u8)bfin_read16(addr) # undef writeb # define writeb(b, addr) bfin_write16(addr, b) +# undef MUSB_TXCSR_MODE /* not supported */ +# define MUSB_TXCSR_MODE 0 /* * The USB PHY on current Blackfin processors is a UTMI+ level 2 PHY. * However, it has no ULPI support - so there are no registers at all. |