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| author | Bob Feretich <bob.feretich@rafresearch.com> | 2011-02-24 13:16:44 +0000 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-09-04 11:36:19 +0200 |
| commit | 52d82e40b0332119d14f206555863c77b4f5edb3 (patch) | |
| tree | b280b149c3f460133f3c6988412f7c5eedb7468e | |
| parent | 0f3d6b06ea06e5b0295e4a8222a25bc95a70c026 (diff) | |
| download | u-boot-imx-52d82e40b0332119d14f206555863c77b4f5edb3.zip u-boot-imx-52d82e40b0332119d14f206555863c77b4f5edb3.tar.gz u-boot-imx-52d82e40b0332119d14f206555863c77b4f5edb3.tar.bz2 | |
OMAP3 Beagle Pin Mux initialization glitch fix
The below patch reverses the order of two segments in the board file.
Output pins need to have their values initialized, before they are
exposed to the logic outside the chip.
Signed-off-by: Bob Feretich <bob.feretich@rafresearch.com>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
| -rw-r--r-- | board/ti/beagle/beagle.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index ab50514..15d061a 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -301,17 +301,17 @@ int misc_init_r(void) twl4030_power_init(); twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); - /* Configure GPIOs to output */ - writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); - writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | - GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); - - /* Set GPIOs */ + /* Set GPIO states before they are made outputs */ writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1, &gpio6_base->setdataout); writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + /* Configure GPIOs to output */ + writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe); + writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | + GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe); + dieid_num_r(); return 0; |